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Everything posted by mooredan

  1. I'm looking for best known practices for mananging UVM tests with Synopsys VCS. What I would like to do is to compile the testbench once and then simulate the different test cases in the same directory. For example, the test package contains test1, test2, and test3 (all extended from the base_test (extended from uvm_test class)). So the command lines after compilation would be: ./simv +UVM_TESTNAME=test1 -l simv.test1.log ./simv +UVM_TESTNAME=test2 -l simv.test2.log ./simv +UVM_TESTNAME=test3 -l simv.test3.log This can easily be placed in a shell script loop or a Ma
  2. Hi all. This is my first post here and I'm learning UVM, but I'm not new to verification or SystemVerilog. I've seen three examples of integrating uvm_reg_block objects into a test bench. two of them (jellybean and verificationacademy) create the extended uvm_reg_block object in the test object, whereas doulos creates it in the top level env (above the agent env). For a hierarchical point of view, the latter location seems to make the most sense. However, it seems that there's a bunch of hoops to jump through to get it working. From a ease of use sense, creating it in the test ob
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