kkibria

Hi Mark: In such case I need a bit more clarification. I will use the following example, let me know if my bit order assumptions are correct. Lets say the port is [3:0][2:0][1:0] portname; Example 1: If the range is not specified then the width of the default value has to be 4x3x2 = 24. Default value bit ordering, leftmost ---- rightmost portname[3][2][1], portname[3][2][0], portname[3][1][1], portname[3][1][0] ---- portname[0][0][0] Example 2: If the range is specified = [2:1] then the width of the default value has to be 2x3x2 = 6. Default value bit ordering, leftmost ----

Hello folks: I am referring to IP-XACT 1685-2014 standard, but may be applicable to earlier versions as well. Component wire ports can have multiple drivers. The each driver has an optional range (section 6.12.10.1) which can only be one dimensional. This works alright for one dimensional ports. However the standard also allows for declaring multidimensional component ports with arrays (6.12.7.1) and vectors (6.12.8.1). How do I interpret the driver range within the context of multidimensional ports? It seems like default value can be specified for a slice of an standard verilog port.