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Posts posted by manuelselva

  1. Hi all,


    In the context of a very large hardware design simulated in SystemC, we faced some issues with the large footprint of our simulator. After deep and long memory profiling we identified a potential large memory optimization by removing the unique names of each sc_object.


    To assess the footprint saving coming from this optimization, we tweaked the Accellera kernel implementation to remove unique name generation for objects having an automatically generated name (such as signals) and also we removed the check for name uniqueness. The results were good, in the sense that we were able to save around 17 percent of the total memory footprint for a simulation counting more 3.000.000 of sc_objects.


    So my questions are the following ones.


    1. Why does the SystemC standard requires (page 124) that "Each sc_object shall have a unique hierarchical name reflecting its position in the object hierarchy" ? I guess this is only for debug purposes, right ?
    2. Would it be possible to have a runtime option allowing the Accellera kernel implementation to disable this "debugging" feature for in "production" simulators ?


    Thank you for any answers and comments you may have on this topic,





    PS: this work has been recently published at under the title "Speed And Accuracy Dilemma In NoC Simulation: What about Memory Impact?" and will be available soon.

  2. Hi all,


    In the context of a SystemC simulation with many SC_THREAD processes (> 32000), I am facing the following error on an Intel X86 platform running Ubuntu 15.04:


    sc_cor_qt.cpp:114: virtual void sc_core::sc_cor_qt::stack_protect(bool) Assertion `ret == 0' failed


    I looked into the implementation of the kernel, and here is my current understanding.


    The default implementation of the SystemC kernel uses user-level threads (also called coroutines) to implement the SystemC processes. The static processes (SC_THREAD and SC_CTHREAD) are initialized in the sc_simcontext.cpp line 759 thread_p->prepare_for_simulation() This function will create the user-level thread object and then enable stack protection.


    The stack of the user-level thread is allocated in the heap of the SystemC simulation process by the following line


    cor->m_stack = new char[cor->m_stack_size]


    The issue I am facing happens in the stack protection function after the creation, that uses an mprotect system call to make the page just after the stack of the user-level thread (again, being in the heap of the Linux process) non accessible at all (PROT_NONE). The error (ENOMEM) I have from mprotect says that this page we want to protect has never been mapped into the process or that the kernel was not able allocate some internal structures while running the mprotect call. Unfortunately I am not able to know which of these two errors happens and how to fix it. Moreover, I can't see where this extra page is allocated in the heap of the Linux process before the mprotect call is made.


    Does anyone know what is going and/or what can I do know to further debug this issue ?


    Thank you very much for any help you cna provide on this issue ?





  3. Hi,


    In the context of a research project we plan to deliver a simulator based on the SystemC standard. To compile and run the simulator, we suggest the users to use the Accellera implementation. We are now wondering under which open source licences our simulator could be released.  Can we make our software released under BSD, or GPL ? If not, which other licence/s should we use ?


    Thank you,




  4. Hi,


    In my systemc design, I am making high level abstractions about my system. I am not considering at all the time required to transfert information from one module to another. In this case, what are the arguments of not using "standard C++" communication means to let my modules exchange this information ? Do these arguments exist meaning that it's better choiche to go to ports and channels even in this case ?


    Thank you for your help,




  5. In my SystemC design I would like to execute a process at a particular time provided on the command line by end user. What is the proper way to handle that ? I can think of creating an SC_THREAD and waiting for the specified amount of time in the thread, but I am almost sure that there is a cleaner solution for that.


    Thank you for help,




  6. Hi all,


    I tried without succes to replace a 2D array of sc_signal<bool> by a vector<vector<sc_signal> >

    After deep investigations I found the sc_vector class. What is the purpose of SystemC sc_vector class ? What are the missing points in SystemC classe for not being able to use STL vector class to make containers of sc_signal for example ?




  7. Hello all,


    In the standard it's specified that a SystemC implementation "if a specific version of a specific implementation runs a specific application using a specific input data set, the order of process execution shall not vary from run to run".


    I am getting non deterministic results for a particular SystemC application, and before digging into the details of its implementation, I wanted to know wether or not the Accellera standard implementation ensures this point ?


    Moreover I would be interested to know what specific situations may lead to non determinism in SystemC ?


    Thank for any help on this,




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