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manuelselva

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About manuelselva

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  1. Hi Guillaume, Thank you for the reply and the information. Please let us know the progresses you are making on this topic. ---- Manu
  2. Hi all, In the context of a very large hardware design simulated in SystemC, we faced some issues with the large footprint of our simulator. After deep and long memory profiling we identified a potential large memory optimization by removing the unique names of each sc_object. To assess the footprint saving coming from this optimization, we tweaked the Accellera kernel implementation to remove unique name generation for objects having an automatically generated name (such as signals) and also we removed the check for name uniqueness. The results were good, in the sense that we were abl
  3. The answer was already on this forum, but I didn't found it this morning: http://forums.accellera.org/topic/1864-sc-cor-qtstack-protect/ I needed to increase the maximum number of memory mappings allowed by my Linux kernel sudo bash -c 'echo 131060 > /proc/sys/vm/max_map_count' Thank you (by transitivity) Philipp
  4. Hi all, In the context of a SystemC simulation with many SC_THREAD processes (> 32000), I am facing the following error on an Intel X86 platform running Ubuntu 15.04: sc_cor_qt.cpp:114: virtual void sc_core::sc_cor_qt::stack_protect(bool) Assertion `ret == 0' failed I looked into the implementation of the kernel, and here is my current understanding. The default implementation of the SystemC kernel uses user-level threads (also called coroutines) to implement the SystemC processes. The static processes (SC_THREAD and SC_CTHREAD) are initialized in the sc_simcontext.cpp line
  5. Hi all, any suggestion on this question ? Maybe a better place to ask it ? Thank you very much
  6. Hi, In the context of a research project we plan to deliver a simulator based on the SystemC standard. To compile and run the simulator, we suggest the users to use the Accellera implementation. We are now wondering under which open source licences our simulator could be released. Can we make our software released under BSD, or GPL ? If not, which other licence/s should we use ? Thank you, ---- Manuel
  7. Hi, In my systemc design, I am making high level abstractions about my system. I am not considering at all the time required to transfert information from one module to another. In this case, what are the arguments of not using "standard C++" communication means to let my modules exchange this information ? Do these arguments exist meaning that it's better choiche to go to ports and channels even in this case ? Thank you for your help, ----- Manu
  8. In my SystemC design I would like to execute a process at a particular time provided on the command line by end user. What is the proper way to handle that ? I can think of creating an SC_THREAD and waiting for the specified amount of time in the thread, but I am almost sure that there is a cleaner solution for that. Thank you for help, ----- Manu
  9. Hi all, I tried without succes to replace a 2D array of sc_signal<bool> by a vector<vector<sc_signal> > After deep investigations I found the sc_vector class. What is the purpose of SystemC sc_vector class ? What are the missing points in SystemC classe for not being able to use STL vector class to make containers of sc_signal for example ? ------- Manu
  10. Thank you ! (I was looking for that in teh standard documentation instead of looking at the specific implementation one)
  11. Hi, I am using the Accellera SystemC kernel and was wondering if there is some API function to disable the version message printed on stderr when the simulation start ? Manu
  12. Hi Alan, Thank you very much for the quick answer. It confirms what I think, and I would have to look more into the details of the application source to find the standard source of randomness (may be I am adding iteration over a map to the ones you mentioned). Regards, --------- Manuel
  13. Hello all, In the standard it's specified that a SystemC implementation "if a specific version of a specific implementation runs a specific application using a specific input data set, the order of process execution shall not vary from run to run". I am getting non deterministic results for a particular SystemC application, and before digging into the details of its implementation, I wanted to know wether or not the Accellera standard implementation ensures this point ? Moreover I would be interested to know what specific situations may lead to non determinism in SystemC ? Than
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