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dilawar

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  1. Like
    dilawar reacted to David Black in Heartbeat, clock and negedge   
    You can use it however you like. We didn't use it everywhere and I'm sure there are more areas where it might be applicable. The main point is that "Performance is a function of simulator CPU activity and how well it used." In some cases such as clocks, there is a lot of activity that goes unused. Many designs really only use the positive edge of the clock. In some designs, the activity can even be reduced significantly.
    Another instance is timers that often are only touched when they are set up and timeout after N clocks. The RTL approach to modeling a timer decrements the timer value on every clock. A behavioral approach would be:
    void set_timer( int N ) { assert( N > 0 ); delay = N * clock.period(); setup_time = sc_time_stamp(); projected_time = setup_time + delay; timeout_event.notify( delay ); }  The current value of the timer can always be had with:
    int get_timer_value( void ) { return ( projected_time - sc_time_stamp() ) % clock.period() ); } So you really don't even need the clock in many instances. Instead replace clock.period() with a simple constant.
    Fast and smart SystemC models don't use sc_clock at all.
  2. Like
    dilawar reacted to maehne in Making a port optional   
    If you don't use the member functions added that were added for convenience to `sc_in`, `sc_out`, and `sc_inout` to, e.g., call `read()`, `write()`, and the event member functions via the `.` operator than via the corresponding member function in the interface accessed via the `->` operator, you might be able to avoid entirely the derivation of new port classes. Instead, you could simply use a template alias, which was introduced with C++'11:
    template<typename T> using sc_in_opt = sc_core::sc_port<sc_signal_in_if<T>, 1, SC_ZERO_OR_MORE_BOUND>; template<typename T> using sc_inout_opt = sc_core::sc_port<sc_signal_inout_if<T>, 1, SC_ZERO_OR_MORE_BOUND>; template<typename T> using sc_out_opt = sc_core::sc_port<sc_signal_inout_if<T>, 1, SC_ZERO_OR_MORE_BOUND>; If you want to also provide all member functions of `sc_in`, `sc_out`, and `sc_inout`, you will have to derive from the `sc_port` class and implement the full interface as defined in IEEE Std 1666-2011. 
  3. Like
    dilawar reacted to ralph.goergen in can't instantiate sub-modules using vector `port not bound` error   
    Hi.
     
    This is because an unbound port cannot be read.
    A port forwards all read and write calls to the actual interface (signal) it is bound to. In you module constructor, you are still in the model set up and elaboration phase. The port is not yet bound to any signal. Hence, you cannot read from it. Accessing ports should not be done befor end-of-elaboration.
     
    Greetings
    Ralph
  4. Like
    dilawar reacted to Philipp A Hartmann in Binding sca_in ports in a vector   
    You need to create the ports while the correct instantiation context is established.  Since you can't do so during construction of the module, you need to defer it to the 'before_end_of_elaboration()' callback of SystemC.  For this matter, you need to temporarily store the signals, in e.g. a vector of pointers.  See the following (untested) sketch:
    SCA_TDF_MODULE(waste) { sca_tdf::sca_in<double> in; // Main 'in' port sc_core::sc_vector< sca_tdf::sca_in<double> > secondary_ins; // prefer sc_vector over vectors of pointers SCA_CTOR(waste) : in("in"), secondary_ins( "secondary_in" ) { } // temporarily store signal pointer void bind(sca_tdf::sca_signal<double> &s) { sc_assert( sc_core::sc_get_status() == sc_core::SC_ELABORATION ); secondary_signals.push_back( &s ); } void processing() { //... } private: // actually do the binding virtual void before_end_of_elaboration() { // create the secondary ports secondary_ins.init( secondary_signals.size() ); // bind the ports for( std::size_t i = 0; i < secondary_ins.size(); ++i ) secondary_ins[i].bind( *secondary_signals[i] ); // cleanup temporary signals secondary_signals.clear(); // be nice and call the base class callback sca_tdf::sca_tdf_module::before_end_of_elaboration(); } // temporarily hold additional inputs during elaboration std::vector< sca_tdf::sca_signal<double>* > secondary_signals; }; Hope that helps,
      Philipp
  5. Like
    dilawar reacted to heisba in Binding sca_in ports in a vector   
    Hi all,
     
    I have been trying to do something that I'm not sure it's possible. I have some TDF modules that are connected to each other by sca_in and sca_out ports. All of this modules will have at least one of each in/out ports. My idea was that maybe some of them will have some extra in/out ports. For example, if I want two TDFs outputs to go to one TDF input, it is not possible using just one port. Instead, those TDF modules would have a vector of sca_in's so, if I need an extra port, this will be initialized and bound to a signal.
     
    All this is already done and compiling. My problem is that when I initialize and bind that new port, it is not specifically assigned to a TDF so I get this error: "Error: (E100) port specified outside of module: port 'sca_tdf_in_0' (sc_port_base)". I understand the reason of this error, but I would like to know if it is possible to assign this port to its TDF.
     
    Here I will show my code, maybe it's helpful.
     
    class 'gen' is a generator of doubles. It sends an increasing double through its 'out' port.
    class 'pass' is just getting whatever comes from its 'in' port and sending it out through its 'out' port.
    class 'waste' is where the 'magic' may be. Receives whatever which is coming from 'pass'.
     
    main.cpp:
    #include <systemc-ams> #include "gen.h" #include "waste.h" #include "pass.h" int sc_main(int argc, char *argv[]) { gen g("g"); pass p("p"); pass p2("p2"); waste w("w"); sca_tdf::sca_signal<double> sig("sig"); sca_tdf::sca_signal<double> sig2("sig2"); sca_tdf::sca_signal<double> sig3("sig3"); g.out(sig); p.in(sig); // Both 'p' and 'p2' receive from the same signal 'sig'. p2.in(sig); // This works perfectly. p.out(sig2); // The out port of both are bound to different signals. p2.out(sig3); // Otherwise, I would get an error. w.in(sig2); // This is a normal binding (to 'p' and 'sig') that works just fine. w.bind(sig3); // Here's where I want to implement my idea. Look at 'waste.h' sc_core::sc_start(500.0, sc_core::SC_MS); sc_core::sc_stop(); return 0; };  waste.h:
    #ifndef WASTE_H #define WASTE_H #include <systemc-ams> #include <vector> SCA_TDF_MODULE(waste) { sca_tdf::sca_in<double> in; // Main 'in' port std::vector<sca_tdf::sca_in<double>*> secondary_ins; // Vector of extra 'in' ports std::vector<sca_tdf::sca_in<double>*>::iterator it; // Iterator int ins; // Number of extra 'in' ports SCA_CTOR(waste) { it = secondary_ins.begin(); ins = 0; } // This initializes the extra 'in' port and adds it to the vector // Here should go the 'assignation' if it is possible. void new_in() { sca_tdf::sca_in<double> *sec_in = new sca_tdf::sca_in<double>(); secondary_ins.insert(it, sec_in); ins++; } // This method is called in 'main.cpp' and it might assign // the new 'in' port to the given signal void bind(sca_tdf::sca_signal<double> &s) { new_in(); secondary_ins.at(secondary_ins.size()-1)->bind(s); } void processing() { double d = in.read(); std::cout << name() << " - main_in : " << d << std::endl; for(int i=0; i<secondary_ins.size(); i++) { double d2 = secondary_ins.at(i)->read(); std::cout << name() << " - sec_in(" << i << "): " << d2 << std::endl; } } }; #endif So basically that's it. Any ideas? Is it even possible?
     
    Thanks a lot
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