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  1. Thank you for this. Are there any list of guidelines you would suggest for improving simulation performance?
  2. Thanks. This is informative hint. cheers, Dilawar
  3. Hi, I am dynamically populating a network of SC_MODULES inside a global modele `net`. As soon as I create a module `x`, I bind all ports to x (say `a` and `b`) to `sc_signal` x.a and x.b in `net`. When I simulate, all SC_MODULEs run independently and I can see values of `sc_signal`s changing when port value changes. So far so good! This has the advantage and end-user does not have to bind all the ports (many of them are really not essential). Now I wish to connect port `a` and `b` of module `x` to port of `m` and `n` of module `y`. Any new binding will raise an error since I am allowing maximum of 1 binding. I can change the number of binding to 2 but I am not sure if it will cost me run time penalty. If penalty is not significant I can go with this. Anyway I was wordering, how can delete the previous binding on port `m` and `n`? Deleting the signal `y.m` and `y.n` is sufficient? If it is not possible, I'll think of something else.
  4. Thank you maehne. I'll use the `sc_port` solution. It clearly marks my intention in declaration. cheers, Dilawar
  5. https://www.doulos.com/knowhow/systemc/new_standard suggests to do the following. sc_port<i_f, 1, SC_ZERO_OR_MORE_BOUND> opt_port; I am trying to replace some of my `sc_out` and `sc_in` with optional ports. I would like to replace them with `sc_out_opt` and `sc_in_opt` class in headers of my modules. What is the best way to derive these classes such that my code-base works with minimal changes to code? 1. Should I derive them from `sc_port<i_f, 1, SC_ZERO_OR_MORE_BOUND>` or `sc_in` and `sc_out` classes? 2. Can I force a port policy on `sc_in` and `sc_out` in module constructor? Any other suggestions?
  6. Ah, I think I used `input()` in constructor, that is why. But I don't understand why this would be a problem. Removing that call seem to fix the problem though.
  7. Hi, I have two files. In header file I have two modules `camkii` and `camkii_ring`. The `camkii_ring` contains N number of `camkii` submodule. I thought of using std::vector to instantiate the submodules. See the code below. #ifndef CAMKII_H #define CAMKII_H #include <systemc.h> #include <vector> using namespace std; SC_MODULE(camkii) { sc_in_clk clock; sc_in<double> ca_conc_in; sc_signal<double> v1, v2, v3; void init() { cout << "[Ca] " << ca_conc_in << endl; //cout << sc_get_time_resolution() << endl; } void compute_rate() { // do something } SC_CTOR(camkii) { init(); SC_METHOD(compute_rates); sensitive << clock.pos(); } }; /* * This module is a ring of CamKII holoenzyme. It has total of 6 camkii * holoenzymes. */ SC_MODULE( camkii_ring ) { sc_in_clk clock; sc_in<double> ca_in; /* It has 6 subunits of holoenzymes */ vector<camkii*> subunits; void init() { for( int i = 0; i < 6; i++) { stringstream name; name << "sub" << i; camkii* c = new camkii(name.str().c_str()); c->clock(clock); c->ca_conc_in(ca_in); subunits.push_back(c); } } void compute() { } SC_CTOR(camkii_ring) { init(); SC_METHOD(compute); sensitive << clock.pos(); } }; #endif /* end of include guard: CAMKII_H */ And here is my main.cc file. #include "camkii.h" #include <systemc.h> #include <iostream> using namespace std; int sc_main(int argc, char** argv) { sc_clock clock_("GlobalClock", 10, SC_MS, 0.5); sc_signal<double> ca_conc, i1p_conc; sc_signal<double> camkii_out; /* connect the camkii ring to ports */ camkii_ring camkii_ring("cakii_ring"); camkii_ring.clock(clock_); camkii_ring.ca_in(ca_conc); cout << "Starting ..." << endl; sc_start(100, SC_MS); return 1; } It compiles fine but when I run it Error: (E112) get interface failed: port is not bound: port 'cakii_ring.sub0.port_1' (sc_in) In file: sc_port.cpp:230
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