
dilawar
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dilawar started following Heartbeat, clock and negedge
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Thank you for this. Are there any list of guidelines you would suggest for improving simulation performance?
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dilawar reacted to a post in a topic: Heartbeat, clock and negedge
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Thanks. This is informative hint. cheers, Dilawar
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Hi, I am dynamically populating a network of SC_MODULES inside a global modele `net`. As soon as I create a module `x`, I bind all ports to x (say `a` and `b`) to `sc_signal` x.a and x.b in `net`. When I simulate, all SC_MODULEs run independently and I can see values of `sc_signal`s changing when port value changes. So far so good! This has the advantage and end-user does not have to bind all the ports (many of them are really not essential). Now I wish to connect port `a` and `b` of module `x` to port of `m` and `n` of module `y`. Any new binding will raise an error since I am allo
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Thank you maehne. I'll use the `sc_port` solution. It clearly marks my intention in declaration. cheers, Dilawar
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dilawar reacted to a post in a topic: Making a port optional
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dilawar reacted to a post in a topic: can't instantiate sub-modules using vector `port not bound` error
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https://www.doulos.com/knowhow/systemc/new_standard suggests to do the following. sc_port<i_f, 1, SC_ZERO_OR_MORE_BOUND> opt_port; I am trying to replace some of my `sc_out` and `sc_in` with optional ports. I would like to replace them with `sc_out_opt` and `sc_in_opt` class in headers of my modules. What is the best way to derive these classes such that my code-base works with minimal changes to code? 1. Should I derive them from `sc_port<i_f, 1, SC_ZERO_OR_MORE_BOUND>` or `sc_in` and `sc_out` classes? 2. Can I force a port policy on `sc_in` and `sc_out` in m
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dilawar reacted to a post in a topic: Binding sca_in ports in a vector
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dilawar reacted to a post in a topic: Binding sca_in ports in a vector
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can't instantiate sub-modules using vector `port not bound` error
dilawar replied to dilawar's topic in SystemC Language
Ah, I think I used `input()` in constructor, that is why. But I don't understand why this would be a problem. Removing that call seem to fix the problem though. -
Hi, I have two files. In header file I have two modules `camkii` and `camkii_ring`. The `camkii_ring` contains N number of `camkii` submodule. I thought of using std::vector to instantiate the submodules. See the code below. #ifndef CAMKII_H #define CAMKII_H #include <systemc.h> #include <vector> using namespace std; SC_MODULE(camkii) { sc_in_clk clock; sc_in<double> ca_conc_in; sc_signal<double> v1, v2, v3; void init() { cout << "[Ca] " << ca_conc_in << endl; //cout << sc_get_time_reso