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  1. thanks if i want to initialize counterval to zero that count begin from zero waht can i do?
  2. i want to consider capability to synthesis of sample systemc code whit agility compiler i faced this error aall (E1064) Ports of type sc_bit are not allowed systemc.h Line:324 Col:13 ag_util.h Line:33 Col:12 header.sc.h Line:1075 Col:2 synthesis.sc.cpp Line:6 Col:5 synthesis.sc.cpp Line:3 Col:6
  3. Hi the output is here #include "systemc.h" // define counter SC_MODULE(counter) { sc_in_clk clk; sc_in <bool> clear; sc_out <sc_lv <4> > dout; int countval; void onetwothree(); SC_CTOR(counter) { SC_METHOD(onetwothree); sensitive<<clk.pos(); } }; void counter::onetwothree() { if (clear) countval = 0; else countval++; dout = countval; } /////////////////////// //define dec SC_MODULE (dec_4){ sc_in_clk clk; sc_in< sc_lv<4> > in_d; sc_out< sc_lv<16> > out_d; void process() { if (in_d.read() ==
  4. if i use wait and while i get a reasonable response but if i use SC_METHOD get wrong response. and the counter not work. i dont know!
  5. are wait() capable to synthesis in systemc?
  6. Hi i want to manage the flow of the out put ports of the main controller (see figure) for this goal i design a counter and connect it to the decoder the out put of the decoder is T[0] to T[15] for example the order of the ports as follow but this idea is not work ld_dr.write(T.read()[0]); ld_ac.write(T.read()[1]); ld_tr.write(T.read()[2]); ld_ir.write(T.read()[3]); ld_pc.write(T.read()[4]); ld_ar.write(T.read()[5]); ld_ou.write(T.read()[6]); ld_inp.write(T.read()[7]); the code is here #include "systemc.h" // define counter SC_MODULE(counter) { sc_in_clk clk; sc_in <bool>
  7. yes i forgot i must to insert this thak you SC_METHOD(process); sensitive<<bus;
  8. good point sc_unit() is better i use this and problem is solved tank you sc_lv<12> addr_lv = addr.read(); sc_uint<12> add = addr_lv; out1 = ram_data[add]; if(clk){ if (ld) { ram_data[add] = in1; }
  9. Hi i write this sample code in this code i connect two register i want to trace bus_out signal that is between two register with VCD view but in VCD view the value of bus_out signal is xxxx while bus_out must be value! the image of VCD is attached // mahbod #include "systemc.h" // define reg 16 bit SC_MODULE (reg16bit) { sc_in <bool> inc,ld,clr; sc_in <sc_lv <16> > in16; sc_out <sc_lv <16> > out16; sc_in <bool> clk; void reg_func (); SC_CTOR (reg16bit) { SC_THREAD (reg_func); sensitive << clk.pos(); } }; // define reg function void reg16bit::
  10. Hi is this memory definition is true? SC_MODULE(mem16) { sc_in <sc_lv <16> > in1; sc_out <sc_lv <16> > out1; sc_in <sc_lv <12> > addr; sc_in <bool> ld; sc_in_clk clk; int i; void write_data(); sc_lv <16> ram_data[4096]; SC_CTOR(mem16) { SC_METHOD(write_data); sensitive << addr << ld << in1 << clk ; //memory initialization ram_data[0]="0000000000000001"; ram_data[1]="0000000000000011"; ram_data[2]="0000000000000111"; ram_data[3]="0000000000001111"; ram_data[4]="0000000000011111"; ram_data
  11. Hi i study about softwares that suport systemc in simuation or synthesis. for example c to silicon compiler from cadene. but when i study datasheet of these softwares ,i cant understand some of the features that in these datasheets. i searching the document that explain this features very good but i cant find it. please help
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