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  1. Hello, compiling systemc-ams-2.1 with clang version 7.0.0 using systemc-2.3.3 yields the following error : make[5]: Entering directory '/home/tools/src/sysc/build/src/scams/impl/core' CXX sca_globals.lo CXX sca_interface.lo CXX sca_implementation_info.lo CXX sca_max_time.lo CXX sca_module.lo In file included from ../../../../../systemc-ams-2.1/src/scams/impl/core/sca_module.cpp:40: In file included from ../../../../../systemc-ams-2.1/src/systemc-ams:180: ../../../../../systemc-ams-2.1/src/scams/predefined_moc/tdf/sca_tdf_sc_out.h:549:27:
  2. Hi Karsten, Many thanks for the reply. Regarding your comments on the large example: The code I profiled above has a block something like outlined below: SCA_TDF_MODULE(vco_1f) { sca_tdf::sca_out<double> out; : : sca_tdf::sca_ltf_nd ltf_nd; sca_util::sca_vector < sca_util::sca_vector < double > > num, den; : : }; void vco_1f::initialize() { num(0)(0) = something; num(1)(0) = something_else; : : num(8)(0) = something_else_again; den(0)(
  3. Hi Dakupoto, I'm not really sure why you would not consider simulation speed to be important. I can only refer to my own experience using SystemC AMS for virtual prototyping of a real system to be implemented. The advantage of virtual prototyping is that a number of iterations, architectural changes and detail level refinements etc. can be applied to the model before arriving at an adequate solution that meets the project specification. The longer the virtual prototype takes to execute the less time can be spent to iterate and refine the design. Time being a finite commodity ! The result
  4. profiling on the larger example Flat profile: Each sample counts as 0.01 seconds. % cumulative self self total time seconds seconds calls ns/call ns/call name 6.20 0.67 0.67 sys_rand::mrand() 5.55 1.26 0.60 sca_util::sca_implementation::sca_matrix_base<double>::resize(unsigned long, unsigned long) 4.99 1.80 0.54 sca_tdf::sca_implementation::sca_ct_ltf_nd_proxy::setup_equation_system() 4.94 2.33 0.53
  5. I did run the example I posted using gprof Flat profile: Each sample counts as 0.01 seconds. % cumulative self self total time seconds seconds calls ns/call ns/call name 30.00 0.03 0.03 sca_core::sca_implementation::sca_synchronization_layer_process::wait_for_next_start() 20.00 0.05 0.02 sca_core::sca_implementation::sca_solver_base::get_current_period() 10.00 0.06 0.01 2000000 5.00 5.00 sca_tdf::sca_implementation::sca_tdf_signal_impl<double>
  6. Thanks again for your reply Torsten. You are correct my posted example is extremely simple ! The motivation behind my post was that I'm seeing similar results with much bigger systems, the PLL as mentioned above. The problem with the bigger systems is doing an apples for apples comparison since I haven't been rigorously implementing exactly the same functionality in the same blocks between SystemC AMS and CppSim (I've added additional complexity to the SystemC AMS modules). However, and for what it's worth, for a 100uS run with a 100pS time step I get real 0m28.829s user 0m26.767s sys
  7. Hi, I recompiled the Fraunhofer SystemC AMS code without the -g option as suggested, OPT_CXXFLAGS (which I take to be the optimised CXXFLAGS) is set to "-O3 -g -Wall -pedantic -Wno-long-long", so I'm using -fPIC -O3 -Wall -pedantic -Wno-long-long It makes no difference regards trev
  8. Hi Torsten, Thanks very much for the reply. You are absolutely correct about the I/O, CppSim writes output in hspice compatible binary format. Switching off the output in both yields roughly 700mS for System AMS versus 60mS for CppSim. Compiling the System AMS module with the -O3 option yields a 30% improvement over the raw performance of the simulation (with no I/O), I will take a look at recompiling the SystemC AMS source with the optimised mode. Still, that currently leaves me with nearly an order of magnitude difference in raw simulation speed and no output data ! b
  9. Hi, I've been reading the forum for some time now but this is my first post. I've been using SystemC AMS for mixed signal modelling - mainly fracN PLL's, mixing verilator to generate verilog based systemC modules and SystemC AMS/ System C modules for analog/mixed signal blocks. I have been using CppSim previously for the same tasks. the System C AMS implementation is significantly slower than using CppSim. I've hacked together a really simple VCO (voltage controlled oscillator) model as an example: #include <systemc-ams.h> SCA_TDF_MODULE(con) { sca_tdf::sca_out<double&g
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