For AXI write transaction axi wready signal determines whether the slave can accept the data. For write burst performance i need to capture the latency between "WREADY" and "next WREADY" signal. For example this ready signal is getting low at clockno 8 and it should remain low for clockno 9 and 10 and the clockno 11 the signal will be high as per the slave configuration. when the multiple burst transacion occurs with (write length > 2) the ready signal behavior will be like above. I want to write a functional coverage like "wready" and next "wready" signal latency is 2 which means when the ready signal is low it will low for 2 clk cycles and then ready will high(if there are multiple write burst transaction).