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  1. Thanks for your help. I have read your post and another post from other member which I thought to be relevant http://forums.accellera.org/topic/980-what-is-the-proper-way-to-trigger-something-when-a-uvm-reg-field-is-written/ I do have one more question related to the link you provided. Do you mean that for such purpose I should implement post_predict in callback only? Do I still need to implement corresponding post/pre_write/read methods? (I have bus adapter and predictor hooked on with a bus monitor, and I configure it as explicit prediction by turning off auto_predict.) Kind regards,
  2. Hi, I have implemented a uvm reg block containing several uvm reg's. What I want to model is register reg_a has the following layout: {fld_a, fld_b,fld_c} and register reg_b has: {fld_st,fld_rsv} The read return of reg_a has fld_b and fld_c as is, while the fld_a value of read data is dependent upon the value of reg_b.fld_st: If reg_b.fld_st = 0, the read data of reg_a is {0,fld_b,fld_c} If reg_b.fld_st = 1, the read data of reg_a is unmodified. I think I need a post_read task implemented for reg_a, but could you please let me know where I should put it? The scope of accessing both reg's should be at reg block, but I don't know how to add a callback there to achieve this. An example is much appreciated. Thank you.
  3. Sorry that I did not post the example. Here it is: Hierarchy of design: top.dut.u_reg module u_reg; ... output [31:0] d_o, ... wire [31:0] d; reg a_reg; reg b_reg; reg c_reg; reg d_reg; //Each *_reg has a driver block for updating its value //there are a few combination logic outside always block //Ex: always (posedge clk or negedge rst_n) begin if (!rst_n) a_reg = 0; else if (we_n) a_reg ‹= a_reg_nxt; end decode and value calculation for a_reg here. ... assign d = {28'h0,a_reg, b_reg,c_reg,d_reg}; //d is the register, and there is a output from this module, d_o: assign d_o = d; endmodule I tried to use the following coeds in my reg_block, the d register has objcet name: D_reg: D_reg.add_hdl_path_slice("d", 0, 32); D_reg.add_hdl_path_slice("a_reg", 3, 1); D_reg.add_hdl_path_slice("b_reg", 2, 1); D_reg.add_hdl_path_slice("c_reg", 1, 1); D_reg.add_hdl_path_slice("d_reg", 0, 1); The simulation log does show that the simulation(questasim) can resolve the hdl path, but the write data couldn't get through. The waveform dose not indicate the data changes either. Thanks.
  4. Hi, In rtl design, I have a wire [3:0] d signal. It's assigned with 4 signals declared as reg type. So my question is when I try to add hdl path slice for d what should I do? I tried to add each of the four signals as slices, then in the test backdoor write to d has problem, I can't seem to pass wdata well. Ex: env. rm. d. write(...UVM_BACKDOOR) doesn't work. The d is a register naming which I create a uvm reg for it. Any input is appreciated.
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