The fundamental problem with doing this kind of thing is that SystemC doesn't have any real concept of drivers and receivers and how to mix driver/receiver types on a wire.
Having said that you can usually bridge stuff with PLI/VPI/DPI code - which is more portable anyway. You just hook-up/create your SystemC during initialization rather than doing the "foreign" module thing at elaboration, e.g. paraphrasing Sebs solution:
module my_mod(sig_in, sig_out) input[63:0] sig_in;logic[63:0] sig_in; output[63:0] sig_out; logic[63:0] sig_out;
initial begin
$hook_up_sysc(sig_in,sig_out,<extra args>);
end endmodule
From my perspective simulation is flat and considering one thing or another as being "on top" isn't really helpful other than it defines the namespace, you should be able to add, subtract and rewire stuff as you go (particularly when it's C++). Verilog has hooks for doing that since the simulators usually have to talk to other applications and things like emulators.