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Everything posted by sebs

  1. Regardless of the file_in_tdf module the problem may also occur in case of systems where borders between TDF domains with different time steps are necessary. Nevertheless, the decoupling out ports sound like what I was looking for. I will try it out. Thanks for your help!
  2. I am currently working on a module that equidistantly reads in values from a text file. For this purpose, I use the file_in_tdf module from the basic library of COSIDE and have set the time step to 1s and interpolation to true. The idea now is to have a subsequent module that, however, has a lower time step, let's say 10 ms. Unfortunately I get the following error when trying to simulate: Inconsistency in timestep assignment between module: top. ... .i_file_in_tdf1 timestep: 1 s (1 Hz) expect: 10 ms (100 Hz) and module: top. ... .dummy_inst T: 10 ms (100 Hz) or expect: 1 s (1 Hz) rate1/rate2= 1/1 dT: -990 ms Of course both elements do not have the same time step, but I would expect that the file_in_tdf module is able to provide interpolated values every 10ms. So, is there any additional configuration I have to consider for the file_in_tdf module to have some kind of upsampling? Do I have to add a user-defined module in between which does the job for me or is such a timing setup simply not possible? Kind regards, Sebastian Simon
  3. Thanks a lot for your comprehensive explanations! @Torsten: I tried out your second proposal and it indeed worked! So what I did: I created a SystemC SC_MODULE wrapper with sc_in<double> and sc_out<double> ports and mapped them to sca_tdf::sca_signal<double> via dedicated bridges that have the following ports: SCA_TDF_MODULE(out_bridge) { sca_tdf::sca_in<double> in; sca_tdf::sc_out<double> out; ... } and SCA_TDF_MODULE(in_bridge) { sca_tdf::sc_in<double> in; sca_tdf::sca_out<double> out; ... } @Martin: The main intention is to use a SystemVerilog/UVM test bench on top. So, that's why I wanted to use a Verilog-AMS wrapper. However, I found out that using a simple SystemVerilog wrapper is sufficient in this case, because the interface is purely discrete when connecting it to the aforementioned SystemC wrapper. @Kevin: So, when I get you right $hook_up_sysc is a user-defined function that hooks up the SystemC module via e.g. DPI-C? If so, how would such a hooking look like? Kind regards, Seb
  4. Hi there, I am currently trying to simulate SystemC-AMS models with Incisive and Verilog-on-top. For this purpose I have written a Verilog-AMS wrapper and at first tried to simulate a simple SystemC model with the following ports: #include <systemc> SC_MODULE(my_mod) { sc_in<double> sig_in; sc_out<double> sig_out; ... }; The VAMS wrapper basically looks as follows: `include "disciplines.vams" `timescale 1ns/1ns module my_mod_wrapper (in_if, out_if); input in_if; wreal in_if; output out_if; wreal out_if; real out_ext_temp; reg[63:0] in_ext; wire[63:0] out_ext; assign out_if = out_ext_temp; initial begin in_ext = $realtobits(in_if); end always @(in_if) in_ext = $realtobits(in_if); always @(out_ext) out_ext_temp = $bitstoreal(out_ext); my_mod my_mod_inst(.sig_in(in_ext), .sig_out(out_ext)); endmodule module my_mod(sig_in, sig_out) (* integer foreign = "SystemC"; *); input[63:0] sig_in; logic[63:0] sig_in; output[63:0] sig_out; logic[63:0] sig_out; endmodule However, when changing the port types of my_mod from ... sc_in<double> sig_in; sc_out<double> sig_out; ... to ... #include <systemc-ams.h> ... sca_tdf::sca_in<double> sig_in; sca_tdf::sca_out<double> sig_out; ... in order to have SystemC-AMS ports, the simulator gives the following error message: ncelab: *E,SCK923: No valid SystemC port found in exported SystemC module that matches with HDL port in corresponding shell HDL module: Module name is 'my_mod' Instance name is 'top.my_mod_wrapper_inst.my_mod_dut' Port name is 'sig_in' In file: sc_cosim.cpp:4969. ncelab: *E,SCK954: Error connecting port of SystemC module instantiated in HDL: Module name is 'my_mod' Port name is 'sig_in' In file: sc_cosim.cpp:1446. ncelab: *F,SCIPCF: Could not connect port 'sig_in' for instance 'top.soc_wrapper_inst.my_mod_dut'. irun: *E,ELBERR: Error during elaboration (status 2), exiting. make: *** [run] Error 1 So it seems I cannot simply use this way of connecting double ports to reg/wire types, although sig_in and sig_out are from type double in both cases. What is the best way to connect SystemC-AMS modules to Verilog(-AMS) in my case? Cheers, Seb
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