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Everything posted by hvgbl

  1. can anyone, please provide link from where i can download the vreguvm utility ?? i am using questasim 10.2a.
  2. First of all develop Top file, and instance TEST file in it. than develop another file, and add your functionality (eg. Display, Vairable, etc.) in it. and check the correctness or connectivity between Test or Top file. Than develop sequence item, and randomize it and again check for the display. And proceed in this way.
  3. I want to achieve following logic. Start_Seq -----> Parent Seq -----> Child Seq1 -----> Child Seq2 -----> Child Seq3 i tried following two sequences. MY_REG_SEQ --> Parent Seq TRY_SEQ --> Child Seq But when i execute the below sequences, i get error for bad handle/reference. `include "my_reg_block.sv" class try_seq extends uvm_sequence; `uvm_object_utils(try_seq) my_block block_obj; integer count = 0; function new (string name = "TRY_SEQ"); super.new(name); endfunction: new virtual task body(); uvm_status_e status; uvm_reg_data_t data; uvm_reg_data_t des_data; uvm_reg my_reg[$]; block_obj.get_registers(my_reg); // Getting ERROR FOR BAD HANDLE/ REFERENCE foreach(my_reg[i]) begin des_data[7:0] = $random(); count = count +1; $display($time,"%0d,Hello",count); my_reg[i].write(status, des_data, UVM_BACKDOOR,.parent(this)); end # 25; $display("Transaction Finished"); endtask: body endclass: try_seq `include "my_reg_block.sv" `include "my_adapter.sv" //`include "ram_top.sv" `include "try_seq.sv" class my_reg_seq extends uvm_sequence; `uvm_object_utils(my_reg_seq) try_seq t_seq; my_block block_obj; // Need to take block instance, as we are mapping sequence reg_block with environment reg_block function new (string name = "SEQ"); super.new(name); t_seq = try_seq::type_id::create(.name("t_seq")); endfunction virtual task body(); $display("TRY_SEQ Starting"); `uvm_do(t_seq) #10; endtask: body endclass: my_reg_seq Any other way to achieve this, or please guide me, if i am wrong at some point. Thank you.
  4. Done . In my write method i havnt declared him the parent. my_reg.write (status, des_data, UVM_FRONTDOOR, .parent(this));
  5. When i used following logic. uvm_reg my_reg[$]; block_obj.get_registers(my_reg); foreach(my_reg) my_reg.write (status, des_data, UVM_FRONTDOOR, this); I get following warning and error. Warning: Register block_obj.reg1 is not contained with in map 'my_r_seq' (called from write()). Error: No transactor available to physically access registers on map 'my_r_seq'.
  6. Hello all, Sorry for stupid question. I have my registers defined as, reg1, reg2, reg3.....................reg64. Now i want to drive a single value (ZERO) to all register using for loop. so i implemented, for (integer i = 0; i<65; i = i+1); des_data[0:7] = 8'h00; block_obj.$sformatf("reg%0d",i).write(status, des_data, UVM_FRONTDOOR,.parent(this)); But i am unable to achieve so. Any one else can suggest alternate solution or logic for the above problem ??
  7. Exactly you are right uwes. But my point of confusion was that, dont we have any other method to update the transaction packet ? I mean, INITIALLY my driver class contained a single task, which simple recieves the transaction and send it on iterface. I was not taking response from DUT. But as TIMI suggested, i added a logic which gets back the response from DUT. So now my DRIVER CLASS CODE IS AS FOLLOWS: virtual task drive_sig(my_packet drv_pkt); //Driving the signals on the interface. drv_intf.read_en <= drv_pkt.read_rq; drv_intf.write_en <= drv_pkt.write_rq; drv_intf.ip_add <= drv_pkt.add; drv_intf.write_data <= drv_pkt.write_data; #1; receive_data(); // Recieving transaction generated by DUT. endtask: drive_sig task receive_data(); if (drv_intf.read_en == 1) begin drv_pkt.read_data = drv_intf.read_data; end else drv_pkt.read_data = 'hff; endtask: receive_data So this do imply that, i have implemented MONITOR CLASS functionality in my DRIVER CLASS. For a single RAM DUT, it is OK to have such logic. But for a big design, do i have to implement whole Monitoring Logic (i.e. DUT's Output). uwes any words on above confusion ?
  8. This POST IS FIX. In my driver, i had update the data field after a read transaction. Which reflects the BUS2REG. Thank you everyone, for your precious inputs.
  9. Sir, i also did with set_auto_predict(0). But still facing the issue.
  10. Yes, sir. But you can see from transcript output, i have replied in previous post. The bus2reg called by monitor broadcast executes first. And it returns correct data. (Checked by placing display). Where as when bus2reg called by uvm_reg_map, executes last, and that does not provides correct data. The transcript output at time "35". 35 mo - read_data is 09 // Monitor Snoops the data and broadcast it. # 35PRED - in read data 0000000000000009 | mypl data09 // BUS2REG called by uvm_reg_predictor class, which return 09 value. # 39PRED - in read data 0000000000000000 | mypl data00 // BUS2REG called by uvm_reg_map, which DOES NOT RETURN ACTUAL (09) VALUE. # 39READ SEQ final data 0000000000000000 // Displaying actual data. The connections in environment class are as follows: function void connect_phase(uvm_phase phase); super.connect_phase(phase); block_obj.my_reg_map.set_sequencer(agt_obj.seqr_obj, adpt_obj); // block_obj -> register Block instance, my_reg_map -> register map instance. agt_obj.mon_obj.mon_ap.connect(predictor_obj.bus_in); // agt_obj -> agent class instance, mon_obj -> monitor class instance, mon_ap -> monitor analysis port. predictor_obj.map = block_obj.my_reg_map; predictor_obj.adapter = adpt_obj; //block_obj.my_reg_map.set_auto_predict(0); //block_obj.my_reg_map.set_check_on_read(0); endfunction: connect_phase
  11. Hello Hi. I am facing the same problem rite now. When Monitor sees a particular transaction, it calls the BUS2REG function, which gives correct data/value, But again when it (bus2reg) is called (using READ Method) the data is lost. My Issues is: When i do simple write-read transaction, Using WRITE METHOD the value of a register is written successfully, (I checked using GET() Method). But when i use READ, the monitor receives the DUT output, write it to Analysis Port, and on same time, the BUS2REG is called, which shows correct data value. But that BUS2REG is not called by my READ METHOD, that is called coz of monitor. So when my read sequence starts, the next bus2reg overwrite the previous data value by ZERO. Do you have any solution for the above problem ?? Thank you.
  12. Thankyou sir, But i have defined the registers as RW only. Still facing the problem. The issue i observed is that when i do write-read method. During read method, the bus2reg function is called twice, which overwrites my data. The last third line of below transcript provides me correct address and data. But the second call to bus2reg, overwrites my data and address. And when i use get() method to recheck the data, it will return the correct data stored in my register. :::Transcript::: 0REG2BUS rw,data = 9 at rw,addr = 20 // write sequence started. reg2bus called. # 10value of read_en is 0 // Driver driving the signals on the interface # 10value of write_en is 1 // Driver driving the signals on the interface # 10value of ADD is 20 // Driver driving the signals on the interface # 10value of write_data is 9 // Driver driving the signals on the interface # 10DUT - WR 09 @ 20 // Transaction executed on DUT # 15 mo - read_data is 00 // Monitor gets the previous value of DUT. # 15PRED - in write data 0000000000000000 | mypl data00 // Bus2Reg called once in write condition. # 19PRED - in write data 0000000000000000 | mypl data00 // Bus2Reg called 2nd time in write condition. # 20DUT - WR 09 @ 20 // As i have placed a #10 delay between write and read, the write will executed once again. # 25 mo - read_data is 00 # 25PRED - in write data 0000000000000000 | mypl data00 # 29 # # SEQ READ START // Read Sequence started # 29REG2BUS rw,data = 0 at rw,addr = 20 # 30value of read_en is 1 # 30value of write_en is 0 # 30value of ADD is 20 # 30value of write_data is 0 # 30DUT - RD 09 @ 20 # 35 mo - read_data is 09 # 35PRED - in read data 0000000000000009 | mypl data09 # 39PRED - in read data 0000000000000000 | mypl data00 # 39READ SEQ final data 0000000000000000 # :::Register Block Class::: virtual function void build(); $display("REG_BLOCK -- REG BLOCK BUILD STARTED"); reg1 = my_register::type_id::create("reg1"); reg1.build(); reg1.configure(this); reg2 = my_register::type_id::create("reg2"); reg2.build(); reg2.configure(this); my_reg_map = create_map (.name("my_reg_map"), .base_addr(8'h00), .n_bytes(4), .endian(UVM_LITTLE_ENDIAN)); $display("REG_BLOCK -- REG-MAP CREATED"); my_reg_map.add_reg(.rg(reg1), .offset(8'h10), .rights("RW")); $display("REG_BLOCK -- REG1 CREATED"); my_reg_map.add_reg(.rg(reg2), .offset(8'h20), .rights("RW")); $display("REG_BLOCK -- REG2 CREATED"); lock_model(); endfunction: build
  13. My Register Class: My registers are of RW access policy. class my_register extends uvm_reg; `uvm_object_utils(my_register) rand uvm_reg_field pid; rand uvm_reg_field token; uvm_reg_field reserved; function new (string name = "my_register"); super.new (name, 8, UVM_NO_COVERAGE); endfunction: new virtual function void build(); pid = uvm_reg_field::type_id::create("pid"); token = uvm_reg_field::type_id::create("token"); reserved = uvm_reg_field::type_id::create("reserved"); pid.configure(.parent(this), .size(3), .lsb_pos(0), .access("RW"), .volatile(1), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); token.configure(.parent(this), .size(3), .lsb_pos(3), .access("RW"), .volatile(1), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); reserved.configure(.parent(this), .size(1), .lsb_pos(6), .access("RW"), .volatile(1), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0)); endfunction: build endclass: my_register
  14. Hello Everyone. My question is I can write a register value, but cannot read the same value back. I can get the written value from register by get() method, but when i read the same value, i receive 0, "ZERO". Any solution for this one ? my register sequence is as follows. virtual task body(); uvm_status_e status; uvm_reg_data_t data; $display("\n\n\nTRANSACTION SEQ1 Starting....."); block_obj.reg2.write(status,'h05,UVM_FRONTDOOR,.parent(this)); #09; desired_value = block_obj.reg2.get(); $display($time,"(1)desired_value is %0h",desired_value); $display ($time,"\n\nSEQ READ START"); block_obj.reg2.read(status,data,UVM_FRONTDOOR,.parent(this)); $display ($time,"READ SEQ final data %h\n\n\n",data); desired_value = block_obj.reg2.get(); $display($time,"(2)desired_value is %0h",desired_value); endtask: body
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