Jump to content


  • Posts

  • Joined

  • Last visited

Everything posted by pv.aditya

  1. Thanks to all for your valuable feedback. Am trying to trace my signals to port binding. Will get back soon.
  2. The output of my program says this ... What might be the exact problem.. !! I am unable to tracethat particular port. SystemC 2.2.0 --- Sep 25 2012 13:13:03 Copyright © 1996-2006 by all Contributors ALL RIGHTS RESERVED Info: (I804) /IEEE_Std_1666/deprecated: sc_sensitive_pos is deprecated use sc_sensitive << with pos() instead Error: (E112) get interface failed: port is not bound: port 't1.m1.port_3' (sc_in) In file: ../../../../src/sysc/communication/sc_port.cpp:265 Info: (I804) /IEEE_Std_1666/deprecated: You can turn off warnings about IEEE 1666 deprecated features by placing this method call as the first statement in your sc_main() function: sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
  3. Sir, Can I know where to post the queries. I am stuck with the above problem and am expecting few replies that could help me. Thanks in advance. Aditya PV
  4. Hello all, Am trying to create SPI (serial peripheral interface) and am not using any control, status registers; but inturn am making up two of them , master and slave and give two inputs to both of them and chek the output accordingly ..Am unable to fetch the output. But before that I wanted to just try out data getting transferred from master to slave. The data to be sent is 32 bit data but in chunks of 8 bits. Main_proj.cpp is the main file.. it links up both master as well as slave..!! According to our model, we r thinking to construct a top level module to this master and slave( that is in main_proj.cpp) and send the test inputs to both master as well as slave( to dreg and dreg2 registers via ext and ext1) and achieve a full duplex communication by transferring this data to each other and store them in dreg1 and dreg3 ...!! What do I have to do to enable the communication to happen between master and slave. And I was unable to use read() and write() commands and so used the c++ way of assignment ..! We used systemc v2.2 ..!! Any suggestions would definitely help me. I am a beginner still. So any further explanation or links might be helpful. Thanks in advance. /********* main_cpp.h ***********************************/ #include "master.h" #include "slave.h" int sc_main(int argc, char *argv[]) { sc_core::sc_clock clk("clk", 20, 0.5,0, true); sc_signal<bool> m2,s2; master d1("d1"); //d1.mosi(m1); d1.ext(m2); slave d2("d2"); //d2.miso(s1); d2.ext1(s2); SC_MODULE(top) { sc_in <sc_uint<32> > minput; sc_in <sc_uint<32> > sinput; sc_out <sc_uint<32> > moutput; sc_out <sc_uint<32> > soutput; SC_CTOR(top) { SC_METHOD(top1); sensitive<<clk.pos(); minput= 0xffff; sinput=0x0f0f; } void top1() { m2.write(minput.read); s2.write(sinput.read); } }; d2.dreg3.range(7,0)=(d1.dreg.range(7,0)); d1.dreg1.range(7,0)=(d2.dreg2.range(7,0)); wait(); d2.dreg3.range(15,8)=(d1.dreg.range(15,8)); d1.dreg1.range(15,8)=(d2.dreg2.range(15,8)); wait(); d2.dreg3.range(23,16)=(d1.dreg.range(23,16)); d1.dreg1.range(23,16)=(d2.dreg2.range(23,16)); wait(); d2.dreg3.range(32,24)=(d1.dreg.range(32,24)); d1.dreg1.range(32,24)=(d2.dreg2.range(32,24)); wait(); }; /********* master.h******************************/ #include "systemc.h" SC_MODULE(master) { // port declarations sc_out<sc_uint<8> > mosi; sc_in<sc_uint<8> > miso; sc_in<bool>ss; sc_out<bool> sck; sc_in<bool> clk; // sc_core::sc_clock clk; sc_in <sc_uint<32> > ext; // local variables declaration sc_uint<32> dreg; sc_uint<32> dreg1; //constructor declaration SC_CTOR(master) { wait(); SC_METHOD(mas); sensitive<<clk.pos(); dreg=ext; } //function process void mas() { sck = clk; mosi.write=(dreg.range(7,0).read); wait(); mosi=(dreg.range(15,8)); wait(); mosi=(dreg.range(23,16)); wait(); mosi=(dreg.range(32,24)); wait(); } }; /**************************slave.h*********************/ #include "systemc.h" SC_MODULE(slave) { // port declarations sc_out<sc_uint<8> > mosi; sc_in<sc_uint<8> > miso; // sc_in<bool>ss; sc_in<bool> sck; sc_in<sc_uint<32> > ext1; // local variables declaration sc_uint<32> dreg2; sc_uint<32> dreg3; //constructor declaration SC_CTOR(slave) { wait(); SC_METHOD(slv); sensitive<<sck.pos(); dreg2=ext1; } //function process void slv() { miso=(dreg2.range(7,0)); wait(); miso=(dreg2.range(15,8)); wait(); miso=(dreg2.range(23,16)); wait(); miso=(dreg2.range(32,24)); wait(); } }; /**********************makefile*********************/ export SYSTEMC_HOME=/systemc-2.2.0 g++ -Wno-deprecated -m32 -I. -I$SYSTEMC_HOME/include -c main_proj.cpp export SC_SIGNAL_WRITE_CHECK=DISABLE g++ -m32 -L. -L$SYSTEMC_HOME/lib-linux -o sim main_proj.o -lsystemc -lm ./sim
  • Create New...