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Posts posted by manikanta.mashetti

  1. Thank You Fitch,


    From that thread, I got many things. But few more is


    1. SystemC is mainly used by the system Architects. We also have a tools for RTL modeling (Forte Design Systems Cynthesizer, or Xilinx Vivado HLS) then why the designs are not implemented using SystemC? 


    2. Once the design is also implemented by using SystemC, then it will be very useful to the company with respect to time, money, human forces. But why only people using this language at system level.? Is there any problems with systemC to describe the language at RTL level. 


    3. If we implement the IP in any language, it will be reused in another project(If that same IP comes in to that project also). This is true in any IP. But why Systemc people specially press this point as one of the advantage of Systemc?


    Can you please clarify this ....




    Thanks & regards


  2. Hi ,


    Recently I have studied that SystemC can be used To model High level functional models to detailed clock cycle accurate RTL models.


    If any company done like this then the they can save the time and energy too. Because at different levels we are using the same language.


    But as of my knowledge many companies uses SystemC at system Modeling only.

    Why they are not using the same language at RTL instead it has many advantages. ?


    Please clear this doubt







  3. Thanks for reply,


    Actually I am modelling a processor using system C,


    In this in the ALU (execute stage), one method is there in that depending on the signals coming from the decode stage it triggers, in this case I should  signals in the sensitivity list(other than clock), so here only  I am getting the problem. It triggers more no of times at a same simulation time.


    And I checked with sc_delta_count(), at same simulation time it is giving two count values. How will I resolve this. 

  4. Hello, 


    In system C, A method is called when ever the event in the sensitivity list changes. Like always block in Verilog. Triggering event in sensitive list can be either edge sensitive or level sensitive.


    But at the same simulation time, more than one signal in the sensitivity list changes then that method will be triggered more than once, so at the same simulation time  the method is executed more no of times, where as in verilog always block after all signals finalized it enters in to the block, how will I overcome this problem in systemC.


    Eg:   SC_METHOD(writing_to_memory);



               void  writing_to_memory()






                In the above example at the simulation time of 100ns, data is changed, and address also changed so the method will be called twice and executed twice..But I don't want this type of bahaviour how will implement..


    please help me...

    thank you..

  5. Hi,


    I have some doubts regarding systemC, please help me 



    What are the main advantages of systemC compare to the other modelling languages?


    why architects choose this language ?


    In the Behavioural Modelling how ever we are implementing the functionality using systemC, with this model we can move from netlist to GDSII, but this model is not used for synthesis, and we are again writing the RTL coding and move to the futher steps, why?


    Why many companies are not using SystemC?

  6. Hello sir,


    1.In my module one input,one output ,and input is a float type and the output is sc_bv(bitvector) ,I have done like this.


    sc_in<float> in1;

    sc_out<sc_bv<32>  >out1;

    float temp1;

    sc_bv<32> temp2;



    // Inside the Method process I have written like this







    //But it is showing Error like   request for member 'to_string' in '((check *)this)->check::temp',which is of non class type 'float'.


    //I also tried std::string temp2 instead of bit vector..(shows two number of errors.)


    //what i observed is to_string is applicable to systemC datatypes..But my problem is like above How should I solve this type of conversion...


    Please give the suggestions...

    Thank you.

  7. Thank you philipp,


    1.std::string str1=in1.to_string(SC_BIN) ;


    In this in1 is a unsigned integer data type(assume) ,Iam converting this to binary format and storing in to the str1(string),but here I want to store this str1 in to the bitvector(sc_bv) ,If I do this it shows some error msgs...my task is to assign this string to another variable..which is bitvector..



    2.yes sir ,what you said is corrrect but ,you are converting double to an bit vector ,which is double precision format (64 bits),if I want to use single precision floating point (32 bits) how should I do..?




    If I want to convert  fixed point data type(sc_fixed<32,16>) to sc_bv ...how should I do...?





    Thank you....

  8. Hie,


    1.sc_int<w> , here 'w' can vary from 1 to 64 bits any number you can take,based on your requirement.default is 32 bits


    2.int ,it is a c++ data type it takes by default 32 bits.


    But simulation speed is fast when you use c++ data type compare to the systemC datatype..


    so when you use 32 bits use C++ datatype(int) data type ...else use systemC datatype(sc_int)...

  9. hello,


    Iam a beginner to systemC language..


    1.In systemC ,is there any data type to represent strings ...not a c++ datatypes (char)


    2.How to convert a float datatype to bit vector (or) logic vector (sc_bv/sc_lv) datatype and viceversa.


    3.how to convert a fixed data type(sc_fixed/sc_fix) to the ieee 754 floating point representation..is there any standard data type to represent the floating point datatype in systemC.



    Thanks in advance

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