mivan

Thank you David for the thorough reply.

Hello all, How would one go about leveraging UVM for ES level DUT verification? Most of the stuff from RTL still applies but how do we correctly use the driver and monitor if the DUT does not have signals, but has TLM ports/sockets. The UVM states that one agent should be used per interface, but the problem on the ESL is that there are no signals so how do we monitor TLM ports/sockets with the monitor, while the driver stimulates the DUT? How do we connect ports/exports to the driver, monitor and the DUT simultaneously? A solution without using analysis ports would be great. I've included an image for easier reference. I guess that on ES level the monitor and driver are redundant, but then the sequencer would have to send packets to a checker and the DUT simultaneously, which would require either two ports or an analysis port. Another option would be to keep everything the same as in the image and have two ports, one from the driver to the DUT, and one from the driver to the monitor and send packets simultaneously. Please state your thoughts on this.

I don't know if I'm posting in the right forum section, so I apologize in advance. I have a couple of questions about the UVM-ML architecture. For reference, I will be using the sc-sv unified hierarchy example, which is provided with UVM-ML-1.4.2. 1) In the sctop.cpp file, which looks like this: #include "uvm_ml.h" #include "ml_tlm2.h" #include "producer.h" #include "consumer.h" using namespace uvm; using namespace uvm_ml; // The environment component contains a producer and a consumer class env : public uvm_component { public: producer prod; consumer cons; env(sc_module_name nm) : uvm_component(nm) , prod("prod") , cons("cons") { cout << "SC env::env name= " << this->name() << endl; } void before_end_of_elaboration() { cout << "SC env::before_end_of_elaboration " << this->name() << endl; std::string full_initiator_b_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, tlm_generic_payload, b_isocket , 32); cout << "SC env registered " << full_initiator_b_socket_name << endl; std::string full_initiator_nb_socket_name = ML_TLM2_REGISTER_INITIATOR(prod, tlm_generic_payload, nb_isocket , 32); cout << "SC env registered " << full_initiator_nb_socket_name << endl; std::string full_target_socket_name = ML_TLM2_REGISTER_TARGET(cons, tlm_generic_payload, tsocket , 32); cout << "SC env registered " << full_target_socket_name << endl; } ... UVM_COMPONENT_UTILS(env) }; UVM_COMPONENT_REGISTER(env) // Top level component instantiates env class sctop : public uvm_component { public: env sc_env; sctop(sc_module_name nm) : uvm_component(nm) , sc_env("sc_env") { cout << "SC sctop::sctop name= " << this->name() << " type= " << this->get_type_name() << endl; } ... UVM_COMPONENT_UTILS(sctop) }; UVM_COMPONENT_REGISTER(sctop) #ifdef NC_SYSTEMC NCSC_MODULE_EXPORT(sctop) #else int sc_main(int argc, char** argv) { return 0; } UVM_ML_MODULE_EXPORT(sctop) #endif What is the NC_SYSTEMC define and where is it used? What is UVM_ML_MODULE_EXPORT() and when is it used? 2) In file test.sv: import uvm_pkg::*; `include "uvm_macros.svh" import uvm_ml::*; `include "producer.sv" `include "consumer.sv" ... // Test instantiates the "env" and "testbench" which has a foreign child class test extends uvm_env; env sv_env; testbench tb; ... task run_phase(uvm_phase phase); `uvm_info(get_type_name(),$sformatf("SV test::%s %s", phase.get_name(), get_full_name()),UVM_LOW); while (1) begin #1 uvm_ml::synchronize(); end endtask ... `uvm_component_utils(test) endclass What is the uvm_ml::synchronize() function and when is appropriate to use it? If there are documents where I can find out more please mention them.