mivan

Thank you David for the thorough reply.

Hello all, How would one go about leveraging UVM for ES level DUT verification? Most of the stuff from RTL still applies but how do we correctly use the driver and monitor if the DUT does not have signals, but has TLM ports/sockets. The UVM states that one agent should be used per interface, but the problem on the ESL is that there are no signals so how do we monitor TLM ports/sockets with the monitor, while the driver stimulates the DUT? How do we connect ports/exports to the driver, monitor and the DUT simultaneously? A solution without using analysis ports would be great. I've inclu

I don't know if I'm posting in the right forum section, so I apologize in advance. I have a couple of questions about the UVM-ML architecture. For reference, I will be using the sc-sv unified hierarchy example, which is provided with UVM-ML-1.4.2. 1) In the sctop.cpp file, which looks like this: #include "uvm_ml.h" #include "ml_tlm2.h" #include "producer.h" #include "consumer.h" using namespace uvm; using namespace uvm_ml; // The environment component contains a producer and a consumer class env : public uvm_component { public: producer prod; consumer cons; env(sc_module_na