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qinhailiang

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Posts posted by qinhailiang


  1. We have defined the start_of_simuluation_phase in my testbench class as follow:

    function void start_of_simulation_phase(uvm_phase phase);

    uvm_test_done.set_drain_time(this, 1000000);

    uvm_test_done.set_report_verbosity_level(UVM_HIGH);

    endfunction : start_of_simulation_phase

    Now, we use the +define+UVM_NO_DEPRECATED switch in Makefile file as follow:

    VLOG_OPT = +define+UVM_NO_DEPRECATED

    VLOG = vlog \

    -timescale "1ns/1ps" \

    $(DPILIB_VLOG_OPT) \

    $(VLOG_OPT) \

    $(OPT_C) \

    -mfcu \

    -incr \

    -suppress 2181 \

    +acc=rmb \

    -writetoplevels questa.tops \

    +incdir+$(UVM_HOME)/src \

    $(UVM_HOME)/src/uvm.sv \

    But the simulator reports errors as follow:

    # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=sbi_simple_test -do {do wave.do; run -all; q} -l questa.log -sv_lib ../../../../../uvm-1.1/lib/uvm_dpi itdm_tb_top

    # ** Note: (vsim-3812) Design is being optimized...

    # ** Error: ../../../tb/itdm_ctrl_tb.sv(60): Failed to find 'uvm_test_done' in hierarchical name /uvm_test_done/set_drain_time.

    # ** Error: ../../../tb/itdm_ctrl_tb.sv(61): Failed to find 'uvm_test_done' in hierarchical name /uvm_test_done/set_report_verbosity_level.

    # Optimization failed

    # Error loading design

    Would everyone like to tell how to modify it?


  2. When I simulated the uvm_ref_flow_1.02‘s uart_subsystem by QuestaSim's vsim, it reports error as following:

    # ** Error: (vsim-8322) ../../../../../uvm_ref_flow_1.02/soc_verification_lib/interface_uvc_lib/uart/uart_monitor.sv(66): Covergroup instance option name collision. Duplicate name: 'uart_trans_frame_cg'. <Also see ../../../../../uvm_ref_flow_1.02/soc_verification_lib/interface_uvc_lib/uart/uart_monitor.sv(66)>

    a bit of source codes is copied here:

    66 covergroup uart_trans_frame_cg;

    67 NUM_STOP_BITS : coverpoint cfg.nbstop {

    68 bins ONE = {0};

    69 bins TWO = {1};

    70 }

    71 DATA_LENGTH : coverpoint cfg.char_length {

    72 bins EIGHT = {0,1};

    73 bins SEVEN = {2};

    74 bins SIX = {3};

    75 }

    76 PARITY_MODE : coverpoint cfg.parity_mode {

    77 bins EVEN = {0};

    78 bins ODD = {1};

    79 bins SPACE = {2};

    80 bins MARK = {3};

    81 }

    82 PARITY_ERROR: coverpoint cur_frame.error_bits[1]

    83 {

    84 bins good = { 0 };

    85 bins bad = { 1 };

    86 }

    87

    88 DATA_LENGTH_x_PARITY_MODE: cross DATA_LENGTH, PARITY_MODE;

    89 PARITY_ERROR_x_PARITY_MODE: cross PARITY_ERROR, PARITY_MODE;

    90

    91 endgroup


  3. I have downloaded the phasing_primer_v5.rar from uvm resources column!

    when I try to run it, QuestaSim's vlog gives us the warning as follow:

    QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011

    -- Compiling package uvm_pkg

    -- Compiling package uvm_phase_awareness_pkg

    -- Importing package uvm_pkg

    -- Compiling package blk_a_pkg

    -- Importing package uvm_phase_awareness_pkg

    ** Warning: ../sv/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the

    spelling of the name 'create_item'.

    ** Warning: ../sv/blk_a_seq_lib.svh(162): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the s

    pelling of the name 'start_item'.

    ** Warning: ../sv/blk_a_seq_lib.svh(162): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the

    spelling of the name 'finish_item'.

    ** Warning: ../sv/blk_a_seq_lib.svh(162): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check th

    e spelling of the name 'get_sequencer'.

    -- Compiling package blk_b_pkg

    ** Warning: ../sv/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the

    spelling of the name 'create_item'.

    ** Warning: ../sv/blk_b_seq_lib.svh(162): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the s

    pelling of the name 'start_item'.

    ** Warning: ../sv/blk_b_seq_lib.svh(162): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the

    spelling of the name 'finish_item'.

    ** Warning: ../sv/blk_b_seq_lib.svh(162): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check th

    e spelling of the name 'get_sequencer'.

    -- Compiling package rst_pkg

    -- Compiling package test_pkg

    -- Compiling package test_a_pkg

    -- Importing package blk_a_pkg

    -- Importing package test_pkg

    -- Compiling module top

    -- Importing package test_a_pkg

    -- Importing package blk_b_pkg

    -- Importing package rst_pkg

    Top level modules:

    top

    vsim +UVM_VERBOSITY=UVM_MEDIUM -sv_lib ../../../../../lib/uvm_dpi -do "do wave.do; run -all; q" -l questa.log -f questa.tops +UVM_TESTNAME=test

    Reading C:/questasim_10.0b/tcl/vsim/pref.tcl

    When entering the QuestaSim, the vsim reports errors as follows:

    # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -sv_lib ../../../../../lib/uvm_dpi top

    # ** Note: (vsim-3812) Design is being optimized...

    # ** Error: ../sv/blk_b_seq_lib.svh(159): Failed to find 'create_item' in hierarchical name /create_item.

    # ** Error: ../sv/blk_b_seq_lib.svh(159): Failed to find 'create_item' in hierarchical name /create_item/$$.

    # ** Error: ../sv/blk_b_seq_lib.svh(162): Failed to find 'start_item' in hierarchical name /start_item.

    # ** Error: ../sv/blk_b_seq_lib.svh(162): Failed to find 'finish_item' in hierarchical name /finish_item.

    # ** Error: ../sv/blk_b_seq_lib.svh(162): Failed to find 'get_sequencer' in hierarchical name /get_sequencer.

    # ** Error: ../sv/blk_b_seq_lib.svh(162): Failed to find 'get_sequencer' in hierarchical name /get_sequencer/$$.

    # ** Error: ../sv/blk_a_seq_lib.svh(159): Failed to find 'create_item' in hierarchical name /create_item.

    # ** Error: ../sv/blk_a_seq_lib.svh(159): Failed to find 'create_item' in hierarchical name /create_item/$$.

    # ** Error: ../sv/blk_a_seq_lib.svh(162): Failed to find 'start_item' in hierarchical name /start_item.

    # ** Error: ../sv/blk_a_seq_lib.svh(162): Failed to find 'finish_item' in hierarchical name /finish_item.

    # ** Error: ../sv/blk_a_seq_lib.svh(162): Failed to find 'get_sequencer' in hierarchical name /get_sequencer.

    # ** Error: ../sv/blk_a_seq_lib.svh(162): Failed to find 'get_sequencer' in hierarchical name /get_sequencer/$$.

    # Optimization failed

    # Error loading design

    #

    Who could like to help me?

    Thanks a lot in advance!!


  4. On the page 131 In SV-2009, there is a passage described as follow:

    SystemVerilog provides a mechanism for initializing an instance at the time the object is created. When an object is created, for example,

    Packet p = new;

    The system executes the new function associated with the class:

    class Packet;

    integer command;

    function new();

    command = IDLE;

    endfunction

    endclass

    As show new is now being used in two very different contexts with very different semantics.

    Would everyone like to tell me which are two very different contexts?

    Thanks a lot inadvance!


  5. I want to print every name and id of objects when beding constructed, so i rewrite the new constrcutor of uvm_object.svh as follows:

    function uvm_object::new (string name="");

    m_inst_id = m_inst_count++;

    m_leaf_name = name;

    uvm_report_warning("CONSCTRUCTED", $psprintf("%s being constructed, ID Number is: %d", m_leaf_name, m_inst_id), UVM_NONE);

    endfunction

    it passes the compilation, but questasim exits Abnormally.

    the log file recoder the context as follow:

    # // Questa Sim

    # // Version 10.0b win32 May 5 2011

    # //

    # // Copyright 1991-2011 Mentor Graphics Corporation

    # // All Rights Reserved.

    # //

    # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION

    # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS

    # // LICENSORS AND IS SUBJECT TO LICENSE TERMS.

    # //

    # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test_2m_4s +UVM_PHASE_TRACE -do {run -all; q} -l questa.log -sv_lib ../../../../lib/uvm_dpi ubus_tb_top

    # ** Note: (vsim-3812) Design is being optimized...

    # Loading sv_std.std

    # Loading work.uvm_pkg

    # Loading work.ubus_pkg

    # Loading work.ubus_tb_top(fast)

    # Loading work.dut_dummy(fast)

    # Loading .\../../../../lib/uvm_dpi.dll

    # run -all

    Could everyone like to give me the ways for solution?


  6. is task and function belong to process?

    In SV-2009, section 9.5 refer to as follows:

    9.5 Process execution threads

    SystemVerilog creates a thread of execution for the following:

    — Each initial procedure

    — Each final procedure

    — Each always, always_comb, always_latch and always_ff procedure

    — Each parallel statement in a fork-join (or join_any or join_none) statement group

    — Each dynamic process

    Are task and function belong to process?


  7. when are the codes exectured as follow in uvm_registry.svh:

    local static this_type me = get();

    // Function: get

    //

    // Returns the singleton instance of this type. Type-based factory operation

    // depends on there being a single proxy instance for each registered type.

    static function this_type get();

    if (me == null) begin

    uvm_factory f = uvm_factory::get();

    me = new;

    f.register(me);

    end

    return me;

    endfunction

    whether is it or not in line ' typedef uvm_component_registry #(test,"test") type_id; ' ?

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