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  1. Hi Philipp, Great! Yes, it is better asking for the user input directly instead of pausing. Anyway, I was interested about this sc_pause, so I can do some testing with it. Vielen dank
  2. Hi everybody, I have a simple question (not so sure if the answer is simple too). Is it possible to "pause"/"halt" the simulation temporarily? It would be useful for me in two scenarios: Whenever the simulation reaches a specified point in the code. Just like a breakpoint, but not having the need to use a debugger. So whenever the user presses a key, the simulation goes on. Whenever the simulation reaches a point, where a user needs to send an input. It is similar to the previous one, but the here the user would need to enter an input (int, double, string, etc.). I understand that thi
  3. Hi again! Maybe this is too obvious, but I've been wonderin for a while now and never found the answer (and dared to ask for it ). Is it possible to directly pass whatever comes from an tdf_in port to a tdf_out port? Not only that, is it possible to do it in a sc_module instead of a sca_module? For a better explanation I'll leave a piece of code. Let's say I have: #include <systemc-ams> class some_module : public sc_core::sc_module { public: sca_tdf::sca_in<int> in; sca_tdf::sca_out<int> out; some_module(sc_core::sc_module_name nm); }
  4. Perfect! In the end was that silly problem Thanks a lot, maybe I would never have seen it
  5. Hi all! I have an error that I never had before with AMS. I have a few sc_modules with in and out TDF ports. Inside these sc_modules I have sca_modules, which are connected to those in and out TDF ports. This have been working fine until now, but I created a new class of module exactly the same way as the others and I have this error. I checked in the library and it seems like my sca_module is not assigned to any view: if (view_interface == NULL) { std::ostringstream str; str << "Error: " << name() << " a sca_module must be associated with a concrete view!" <
  6. It works I needed to update my SystemC version (from 2.2 to 2.3), but I finally made it! Thanks a lot Philipp!
  7. Hi all, I have been trying to do something that I'm not sure it's possible. I have some TDF modules that are connected to each other by sca_in and sca_out ports. All of this modules will have at least one of each in/out ports. My idea was that maybe some of them will have some extra in/out ports. For example, if I want two TDFs outputs to go to one TDF input, it is not possible using just one port. Instead, those TDF modules would have a vector of sca_in's so, if I need an extra port, this will be initialized and bound to a signal. All this is already done and compiling. My problem is
  8. I tried that before, the problem is that it is not possible to have a resistor with the value 0 (I get an error). And I think it makes sense, because of the equation (there may be a divisio by zero?). Anyway, I will create a module like that with a very low non-zero value. Thanks again
  9. Lately, I have been dealing with some issues related to the ELN Networks. I am modelling some ELN modules as if they were completely independent, meaning that they can be connected to each other through its terminals no matter what modules it is connected to (considering, of course, the limitations of an ELN network). My problem is that sometimes I would like to have some kind of ELN Cable so I could connect an ELN Node to an ELN Ground (Node Ref), for example. Sounds crazy, but since I am creating a generic way of connecting these modules, sometimes I cannot directly connect a terminal to
  10. I found out that is some kind of loop that I am creating in my module, among the ELN's and TDF's. Setting the vsink in parallel works fine.
  11. Ok, setting the vsink's in parallell with the resistors it works when it comes to the basic ELN. But in the configuration with my sc_modules: node_ref -> vsource -> node -> r -> node -> r -> node_ref |-> vsink ->| |-> vsink ->| I have the following error: I'm still not sure why
  12. Hi Karsten, Thanks for the answer. I may not be using the vsink in a proper way (maybe like isink). As I noted in the previous post, the sequence of my resultant electrical network is this: node_ref -> vsource -> node -> vsink -> node -> r -> node -> vsink -> node -> r -> node_ref If I'm doing it wrong, what should be the proper way to use a vsink and a resistor? Do I have to use a Reference Node instead of a simple node? Thank you again
  13. Hi everyone, I have been working with SystemC-AMS lately and having nice results, but now I'm facing some issues with the sca_eln::sca_tdf::sca_vsink module. I created some sc_modules with ELN modules inside. Quite briefly, the final electrical network (which I get from putting those sc_modules together) that I have been having problems with is: ELN: node_ref -> vsource -> node -> vsink -> node -> r -> node -> vsink -> node -> r -> node_ref SC :|-----GENERATOR-----|->|-----------PIPE-----------|->|----------PIPE------------| -> |---SINK---| I
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