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  1. I am working on a design that supports single, or bursting access to a memory. I would like to keep the abstraction of the register model (ie. MEM.Write(), MEM.bust_write()...). It appears that the register model breaks up the burst-ed writes into single transactions. What is the best way to implement a burst_write (Basically one address, and many data items) into a single seq_item for the driver to implement?
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