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Roman Popov

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Everything posted by Roman Popov

  1. You can report a bug on this forum. Or on github https://github.com/accellera-official/systemc/issues. ../../../../src/sysc/kernel/sc_main.cpp:55: int Check_mprotect(void*, size_t, int): Assertion `ret == 0' failed. I don't see Check_mprotect in sc_main.cpp. Can it be that you have modified SystemC kernel (non-Accellera)? If this is the case you should probably contact support of your SystemC vendor. Why you put extern "C" there? SystemC is C++, and C does not support exceptions. SC_REPORT_FATAL throws exception, and once it reaches your sc_main it is UB (undefined behavior) what happens next. SC_API_PERFORM_CHECK tries to check if SystemC library and user application where compiled with same options and same C++ standard. Looks like exception is thrown when SC_DEFAULT_WRITER_POLICY is configured differently. CentOS 7 supposed to be equivalent to RHEL 7. And RHEL is often used for SystemC development.
  2. No, if you want to keep all ports in same scope you will need to follow Philipp's suggestion.
  3. My advice: start with sc_fifo, learn how it works, learn it's source code. Then write your own handshake channel using same principles.
  4. In general avoid using multiple inheritance for aggregation. It is possible, but has many drawbacks and no major benefits. Now I regret that I've written original post, but at that time I had no enough experience myself. Now, if we read any object oriented design book, we will learn that inheritance usually means "is-a" relation ship, and "has-a" relation ship is expressed by composition. Translating into HW modeling : what we want to express is that "some_module has port bundles", and not "some_module is port bundles". We can still use single inheritance in limited cases, for example if all modules in design have clock and reset, we can have a common base class like class clocked_module : public sc_module Back to your example. I recommend to convert your port bundles into modules: struct if_inputs : sc_module { sc_inout<sc_uint<4>> SC_NAMED(R_OP_MODE); sc_inout<sc_uint<8>> SC_NAMED(R_PRESET_MANUAL); if_inputs(sc_module_name){} }; struct if_outputs : sc_module { sc_inout<sc_uint<2>> SC_NAMED(T_BIT); sc_inout<sc_uint<4>> SC_NAMED(T_OP_MODE); sc_inout<sc_uint<8>> SC_NAMED(T_PRESET_MANUAL); if_outputs(sc_module_name){} }; And now you can aggregate any number of them inside monitor. Even have a vector of port bundles: class monitor : public sc_module { public: if_inputs SC_NAMED(sim_inputs); if_outputs SC_NAMED(sim_outputs); if_inputs SC_NAMED(stub_inputs); if_outputs SC_NAMED(stub_outputs); sc_vector<if_inputs> SC_NAMED(inputs_vector, 3); monitor(sc_module_name name_); private : // implementation details };
  5. SystemC standard does not guarantee any order of process evaluation within a single delta cycle. So in first example both 2,4 and 4,2 will be correct.
  6. They are in namespace sc_core. If you don't want to use namespaces you can change #include <systemc> to #include<systemc.h> and it will pull everything into global namespace.
  7. I mean if you don't need to connect the port, then don't create the port. This is the idea.
  8. Other option is to pass some flag to constructor struct my_module : sc_module { std::unique_ptr< bus_port > bus_slave; my_module(sc_module_name, bool has_slave_port) { if (has_slave_port) { bus_slave = std::make_unique<bus_port>("bus_slave"); } } For SystemC 2.4 there is a sc_optional<T> class proposal that will allow to create ports "on demand" at any time during elaboration.
  9. Clang 5 works fine for me on Linux. This may be a combination of Clang + Cygwin. According to benchmarks https://www.phoronix.com/scan.php?page=article&item=gcc-clang-2019&num=4 compilation time difference for most projects is within 10%.
  10. Clang 8 is quite new compiler and SystemC 2.3.3 was not tested against it. Do you see this issue only in Cygwin? Or in general with Clang 8, including Clang 8 on MacOS / Linux ?
  11. I don't immediately see a problem in code. Just a guess: Have you configured all compiler flags? In case you use CMake it should be automatic. If you create project manually you can check here https://stackoverflow.com/questions/41990606/installing-systemc-for-vs2013/41991699
  12. Clang AST is the best opensource option, but some extra work will be required to support SystemC. With Clang you can quite easily reproduce Pinapa approach. Don't recommend going PinaVM way with using LLVM IR - It is too low level for most SystemC analysis tasks.
  13. Shared libraries and dynamic linker are explained many times on a web, let me google it for you.
  14. Because dynamic linker does not know where to find library. You have two options: use -Wl,rpath,<path/to/lib> command line option at compile time, or set LD_LIBRARY_PATH environment variable. Google for more details.
  15. e.notify(); // immediate notification is executed "immediately" - Thread2 added to set of runnable processes e.notify(3,SC_NS); // e added to kernel event queue, it will be triggered in 3 ns e.notify(3,SC_NS); // e added to kernel event queue to be triggered in 3 ns e.notify(); // previous notification canceled, and instead event is notified immediately, Thread2 added to set of runnable processes
  16. Setting library path != Linking library. Also add -l systemc to g++ options.
  17. Question is too generic. If you have cycle-accurate pin-level model you need to interface with, you will have to write a transactor class that converts functional TLM interface to pin-level protocol. Usually it is implemented as SC_THREAD process sensitive to clock edge.
  18. According to log, you are using C compiler driver (/usr/bin/gcc). SystemC is C++, you should write your application in C++ and use C++ compiler driver (g++). Maybe your IDE automatically uses C compiler because you named your source file main.c
  19. It is configurable, see SystemC standard "6.4.4 Reading and writing signals".
  20. wait(SC_ZERO_TIME); waits for 1 delta cycle I guess you want a clock cycle delay instead. wait( clock.posedge_event() ); // wait until positive clock edge wait( clock.negedge_event() ); // wait until negative clock edge
  21. Please note that event notification will be lost if no one is waiting for it. This may be your case: Option 1: Consumer starts and suspends on wait(), Producer starts, notifies event, resumes consumer. Option 2: Producer starts, notifies event, event notification does nothing since no one is waiting for it. So maybe sc_fifo is what you really need.
  22. Check GCC documentation, likely you need to specify include directories using -I flag https://gcc.gnu.org/onlinedocs/gcc/Directory-Options.html#Directory-Options
  23. You have controversial requirements: a) put stored value when enable == 1 , which sounds like a dff with output_enable b) put input to output when enable == 1, which sounds more like a latch Anyway, in both cases you will need to make process sensitive to enable signal. And usually such low-level logic is modeled with SC_METHODs. In SystemC context "register" usually means some memory-mapped CSR on TLM bus 🙂
  24. What do you mean exactly by "modeling a register"? If you are working on synthesizable code (i.e. using Mentor/Cadence HLS tools), then it is not possible to have 0-delay communication between threads in synthesizable code, as you wanted in original post. At least it was not possible last time I've used these tools. If you are working on some non-synthesizable high-level model, then you can model "register" any way you like, you don't even have to use sc_signal<> for that purpose.
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