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  1. hello, i have jus started working with the systemC implementations for high level synthesis I need to implement the bit slicing paradigm in systemC which i tried with the variable.range() method and it works fine. But when i used with the fixed point types as shown in the code below, it didnt not work. define SC_INCLUDE_FX #include "systemc.h" SC_MODULE(slice){ sc_in<sc_fixed<42,12,SC_TRN,SC_SAT> > input sc_out<sc_fixed<14,14,SC_TRN,SC_SAT> > output void do_slice(){ // output=input.read().range(42,28); //ERROR IN THIS LINE } SC_CTOR(slice){ SC_METHOD(do_slice) sensitive<<input_re; dont_initialize(); } }; then, i tried of casting the fixed to a float / double value and tried to use it with the range method which also didnt work. So the range() method only works with sc_int and sc_uint? Is there any other way to do bit slicing paradigms for fractional values in systemC? please let me know. Thanks in advance
  2. Yes casting explicitly would be the perfect idea. Thanks for pointing it out.
  3. hi all, I am just starting to do some practical implementations in systemC. Here i am trying to do a casting of data type ufixed to uint data type. i have tried the follwing code. #define SC_INCLUDE_FX #include "systemc.h" SC_MODULE(casting){ sc_in<sc_ufixed<8,8, SC_TRN, SC_SAT> > castin; sc_out<sc_uint<8> > castout; void do_cast(){ castout.write(castin.read()); // error in this line } SC_CTOR(casting){ SC_METHOD(do_cast); sensitive<< castin; } }; the problem is, it could not write the ufixed data type on uint type. So how should i do the casting between ufixed and uint data types. Is there any public methods available for this type of casting? or how should i proceed with it. Any ideas and help would be grateful for me. Thanks in advance.
  4. Thanks for the response Alan Fitch, It so thoughtful that you pointed out the problem of FIFO dead lock when the read_en is trying to read a data on empty FIFO . I tested the code changing to nb.read(data) which works fine as expected. and also will try the code the changing the structure as you suggested and let know whether its working.
  5. Is my question clear/ understandable?
  6. Is your vcd file opening in GTK wave viewer? if yes did u try to double click the parameter in SST workspace( on the top left ) on your GTKwave viewer.
  7. Thanks alot Alan Fitch for the response. I tried to clear my fifo with some looping logic as shown below #ifndef FIFO_H_ #define FIFO_H_ #define SC_INCLUDE_FX #include "systemc.h" #include<iostream> SC_MODULE(FIFO){ sc_in<sc_ufixed<8,8,SC_TRN,SC_SAT> > din; sc_in<bool> read_en; // Read enable sc_in<bool> write_en; sc_in<bool> reset; sc_out<sc_ufixed<8,8,SC_TRN,SC_SAT> > dout; sc_out<sc_ufixed<9,9,SC_TRN,SC_SAT> > data_count; sc_fifo<sc_ufixed<8,8, SC_TRN, SC_SAT> > buffer; // FIFO declaration sc_ufixed<8,8,SC_TRN,SC_SAT> temp; void memory_process(){ while(true){ wait(0.2, SC_SEC); temp=din.read(); if (write_en.read()==1){ buffer.nb_write(temp); cout<<"@" << sc_time_stamp()<< " :: write enable is on " << buffer << " Delta count "<< sc_delta_count()<<endl; } else if (read_en.read()==1) { dout = buffer.read(); std::cout<<"@" << sc_time_stamp()<< " :: fifo read occurs" << dout << endl; } if(reset.read()==1) { while(buffer.num_available()!=0){ buffer.nb_read(temp); std::cout<<"@" << sc_time_stamp()<< "::fifo reset is working" << buffer.num_available() << endl; } } data_count= buffer.num_available(); cout<<"@" << sc_time_stamp()<< " :: data count = " << data_count.read() << " delta cycle " << sc_delta_count() << endl; } } SC_CTOR(FIFO) :buffer(512) { SC_THREAD(memory_process); dont_initialize(); sensitive<<din<<read_en<<write_en<< reset; //<<read_en<<write_en; } }; #endif /* FIFO_H_ */ source module #ifndef RNG_H_ #define RNG_H_ #define SC_INCLUDE_FX #include "systemc.h" #include <stdlib.h> //for srand(uint) and rand() #include <iostream> SC_MODULE(rng){ sc_out<sc_ufixed< 8,8,SC_TRN,SC_SAT> > output1; sc_ufixed<8,8,SC_TRN,SC_SAT> A; void process(){ // while(true) { wait(0.2, SC_SEC); // sample time A=rand() % 254 ; // range 0 to 253 output1.write(A); std::cout<<"@" << sc_time_stamp() << " rng output = " << output1 << " delta cycle " << sc_delta_count() <<endl; } } SC_CTOR(rng) { SC_THREAD(process); } }; #endif /* RNG_H_ */ test module #define SC_INCLUDE_FX #include "systemc.h" #include "rng.h" #include "fifo.h" #include<iostream> #include<stdlib.h> int sc_main (int argc, char* argv[]) { sc_buffer< sc_ufixed<8,8,SC_TRN,SC_SAT> > dinsignal; sc_buffer<bool> readen_signal; sc_buffer<bool> writeen_signal; sc_buffer<bool> resetsignal; sc_buffer< sc_ufixed<8,8,SC_TRN,SC_SAT> > doutsignal; sc_buffer< sc_ufixed<9,9,SC_TRN,SC_SAT> > dcountsignal; srand(37); rng r1("rng"); r1.output1(dinsignal); FIFO f1("FIFO"); f1.din(dinsignal); f1.read_en(readen_signal); f1.write_en(writeen_signal); f1.reset(resetsignal); f1.dout(doutsignal); f1.data_count(dcountsignal); readen_signal = 0; writeen_signal =1; resetsignal =0; sc_start(1, SC_SEC); readen_signal = 1; writeen_signal =0; resetsignal =1; sc_start(1, SC_SEC); readen_signal = 0; writeen_signal =1; resetsignal =0; sc_start(1, SC_SEC); return 0; } output @200 ms rng output = 0 @200 ms :: write enable is on 0 @200 ms :: data count = 0 @400 ms rng output = 99 @400 ms :: write enable is on 0 99 @400 ms :: data count = 0 @600 ms rng output = 67 @600 ms :: write enable is on 0 99 67 @600 ms :: data count = 1 @800 ms rng output = 107 @800 ms :: write enable is on 0 99 67 107 @800 ms :: data count = 2 @1 s rng output = 157 @1 s :: write enable is on 0 99 67 107 157 @1 s :: data count = 3 @1200 ms rng output = 212 @1200 ms :: fifo read occurs0 @1200 ms::fifo reset is working3 @1200 ms::fifo reset is working2 @1200 ms::fifo reset is working1 @1200 ms::fifo reset is working0 @1200 ms :: data count = 0 @1400 ms rng output = 167 @1600 ms rng output = 55 @1800 ms rng output = 227 @2 s rng output = 228 @2200 ms rng output = 122 @2400 ms rng output = 82 @2600 ms rng output = 245 @2800 ms rng output = 135 As you can the output @1200ms when fifo reset.read()==1, the fifo clears all the data (reads all the data) at that instant which is working as expected. But after @1200ms no other operations are happening in fifo Even after the resetsignal=0 and writeenable=1 @2000ms, no other operations happening in FIFO. Literally fifo dosent work after reset occurs. can anyone point out what is problem and how to resolve it? thanks in advance
  8. hi all, I have started working in systemC and started with the implementation of a simple FIFO. #ifndef FIFO_H_ #define FIFO_H_ #define SC_INCLUDE_FX #include "systemc.h" #include<iostream> SC_MODULE(FIFO){ sc_in<bool> read_en; // Read enable sc_in<bool> write_en; sc_in<sc_ufixed<8,8,SC_TRN,SC_SAT> > din; sc_in<bool> reset; sc_out<sc_ufixed<8,8,SC_TRN,SC_SAT> > dout; sc_out<sc_ufixed<9,9,SC_TRN,SC_SAT> > data_count; sc_fifo<sc_ufixed<8,8> > buffer; // FIFO declaration sc_ufixed<8,8,SC_TRN,SC_SAT> temp; void memory_process(){ if (write_en.read()==1){ temp=din.read(); buffer.write(temp); cout<<"@" << sc_time_stamp()<< "::write enable is on " << temp << endl; } else if (read_en.read()==1) { dout=buffer.read(); std::cout<<"@" << sc_time_stamp()<< "::fifo read occurs" << dout << endl; } if(reset.read()==1) { buffer.reset(); // } data_count= buffer.num_available(); cout<<"@" << sc_time_stamp()<< "::data count occurs " << data_count << endl; } SC_CTOR(FIFO) : buffer(512){ SC_METHOD(memory_process); sensitive<<din<<read_en<<write_en<< reset; } }; with a simple test bench file i tested the code, the operations regarding read(), write(), num_available() are working as it is supposed to be. but when i tried with reset() method. i am getting the error ' method reset could not be resolved' As per this website http://www.iro.umontreal.ca/~lablasso/docs/SystemC2.0.1/html/structfifo.html it has a public method reset(). so how do i need to do a reset operation in sc_fifo. Any help would be greatly helpful to proceed with the solution Thanks
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