Jump to content


  • Content Count

  • Joined

  • Last visited

  • Days Won


Posts posted by marknoll

  1. Hello Mohamed,


    VHDL configuration information can be specified within the view/modelName element. This is a string which (for VHDL) can specify entity and architecture using the format <entityName>(<architectureName>). If you have multiple architectures, you would have multiple view elements (one per architecture). If you have different file sets for each architecture, then you can specify the files in different IP-XACT fileSets. Then in each view you indicate the appropriate fileSet using the fileSetRef element.


    The "selected" view is documented in the top-level IP-XACT designConfiguration file. That file contains (among other things), a list of viewConfiguration elements which document the selected view for each instance (via the viewName and instanceName elements within the viewConfiguration).




  2. Hi Bernd,


    This is a known issue with the 1685-2009 schema. While the working group was active on development of the upcoming new version of the standard, we agreed to update the 1685-2009 version since the problem was just within the constraints as you indicated. It looks like that update did not occur within the publicly hosted files. I am investigating what is required to make that happen.




  3. Hello Mohamed,


    It is not possible to model conditionality like this in the current version of the standard. However it will be possible in the P1685-2014 version of the standard due out in the Sept/Oct timeframe. It may take some time for tools to support this, but the new version of the standard will definitely support it.


    Regarding the memoryMapRef -- it is not technically required that you reference the memory map via a bus interface, but as you state, if you don't do this there is no way for a tool or IP integrator to know how to reference the memory map.




  4. Hello Mohamed,


    If you mean that you want to indicate that a particular port is a clock port, the typical way to do that would be to define a driver/clockDriver element for the port. This allows you to define the properties of the clock within the port definition. If you are instead asking how to say that a given port is clocked by another port (which is a clock), then there is no explicit way to do that. You could however define a timingConstraint on the port which could link the port to a clock port. Technology independent timing constraints are stored in the constraintSets/constraintSet element within the port. Only technology independent constraints are allowed, as others should be stored in an SDC file and included via fileSet within the component.




  • Create New...