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Everything posted by marknoll

  1. Sorry this thread got dropped. I have had it added to the agenda for the next meeting and am querying within the working group for details. Expect an update here by June 30 as the meeting is on the 29th.
  2. Hard to argue with the premise of this. A good discussion topic for the next TC meeting.
  3. Hello Khan, This is a limitation in the current standard. There is no way to reference anything other than the leftmost dimension of port when defining a driver. Thanks, Mark
  4. Hello Emna, The API is dependent on knowledge of the schema which is not available for vendor extensions. Therefore you do need to process them on the client side (in your code). Thanks, Mark
  5. Hello Emna, You are allowed to do anything you want in a vendor extension as long as it is valid XML. You just need the tool processing the extension to understand the semantics of what you put in the extension. This does not happen automatically. Thanks, Mark
  6. Hi Sachin, Please send me a direct e-mail to mnoll@synopsys.com and I will send you the image directly. Thanks, Mark
  7. The answer depends on which version of the schema you are using. If you are using the 2009 schema, there is no way to get from a component at one level to a lower level component. This is now available in the new 2014 schema. In particular take a look at the new schema in the views.
  8. Hi Amal, I will bring this up at the next IP-XACT meeting and we'll get a plan to resolve. It should be available. Thanks, Mark
  9. Hi RahulJn, The simplest approach would be to use a registerFile with a single register in it. Set the dim on the register file instead of the register, and then use the 'range' on the registerFile to account for the spacing you need. Thanks, Mark
  10. Hi Rahuljn, This is a known bug in the constraints defined for the schema. Since the fix does not impact the schema syntax in any way, we have already independently proposed a fix that should cause an update to the hosted schema files in the near future. Thanks, Mark
  11. Hello Mohamed, VHDL configuration information can be specified within the view/modelName element. This is a string which (for VHDL) can specify entity and architecture using the format <entityName>(<architectureName>). If you have multiple architectures, you would have multiple view elements (one per architecture). If you have different file sets for each architecture, then you can specify the files in different IP-XACT fileSets. Then in each view you indicate the appropriate fileSet using the fileSetRef element. The "selected" view is documented in the top-level IP-XACT de
  12. Hi Bernd, This is a known issue with the 1685-2009 schema. While the working group was active on development of the upcoming new version of the standard, we agreed to update the 1685-2009 version since the problem was just within the constraints as you indicated. It looks like that update did not occur within the publicly hosted files. I am investigating what is required to make that happen. Thanks, Mark
  13. Hello Mohamed, It is not possible to model conditionality like this in the current version of the standard. However it will be possible in the P1685-2014 version of the standard due out in the Sept/Oct timeframe. It may take some time for tools to support this, but the new version of the standard will definitely support it. Regarding the memoryMapRef -- it is not technically required that you reference the memory map via a bus interface, but as you state, if you don't do this there is no way for a tool or IP integrator to know how to reference the memory map. Thanks, Mark
  14. Hello Mohamed, Yes this is the correct syntax. You should be able to confirm this on your side using any XML schema validation tool. Thanks, Mark
  15. Hello Mohamed, If you mean that you want to indicate that a particular port is a clock port, the typical way to do that would be to define a driver/clockDriver element for the port. This allows you to define the properties of the clock within the port definition. If you are instead asking how to say that a given port is clocked by another port (which is a clock), then there is no explicit way to do that. You could however define a timingConstraint on the port which could link the port to a clock port. Technology independent timing constraints are stored in the constraintSets/constraintSet
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