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    ASIC, DV, Functional verification, UVM, System Verilog

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  1. Is there a way to loop over all data attributes in a class declared in SV/UVM, We have something similar in Java: https://stackoverflow.com/questions/3333974/how-to-loop-over-a-class-attributes-in-java The feature would help us implementing data classes.
  2. Hi, Do we have any mechanism in uvm data classes(i.e. any class extended from uvm_transaction) through which we don't allow users to change any attribute of the class object(typically configuration object). I am developing a verification component which has a configuration class and I need to ensure that users are not changing any attributes accidently, if they really need to change anything they should follow a specific protocol so that verification component work as expected all the time. The behaviour of the feature would be something like this: create configuration object, set the attributes as required, once all fields are setup as required assert lock to configuration object(by some method or attribute), after assert users can't modify anything in the configuration unless it gets unlocked. pass it to verification component using uvm_config_db::set() call verification component gets the configuration object using uvm_config_db::get() call if users want to change any configuration attribute at run time, first they need to unlock the configuration object, the unlocking can only be done by the verification component(verification component will ensure that changing the configuration does not impact anything => flush data buffers ....) once unlock by verification component, users can change configuration attributes and set the lock again. BR, Udit
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