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getvictor

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  1. Like
    getvictor got a reaction from sudheervemual in UVM 1.2 Introduction and Code Examples   
    The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference
     
    This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM.
    The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide.
     
    The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher.
    uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon)  
    I hope you find it useful. Let me know what other topics you'd like to see.
     
    Note:
    The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
  2. Like
    getvictor got a reaction from Keypeseep in UVM 1.2 Introduction and Code Examples   
    The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference
     
    This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM.
    The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide.
     
    The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher.
    uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon)  
    I hope you find it useful. Let me know what other topics you'd like to see.
     
    Note:
    The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
  3. Like
    getvictor reacted to tudor.timi in UVM phase singletons   
    Hi,
     
    I remember back in the day in OVM it was possible to say uvm_test_done.set_drain_time(...). With UVM, when compiling with +UVM_NO_DEPRECATED, it's not possible to do this. Phases have their own drain times now. The cool thing about the OVM approach was that I could set the drain time from the end_of_elaboration phase somewhere in my base test and be done with it. I dug around a bit in UVM and found that all phases have singletons. I tried to get a handle to the run phase singleton during the end_of_elaboration phase and set the drain time on that. It didn't work.
     
    All phase methods get a "phase" argument passed to them. I would have expected that this parameter contains already a handle to the phase singleton. I made a small example on EDA Playground (http://www.edaplayground.com/x/2PL) where I get the run phase singleton and print it and also print the argument. They are different objects. Does anyone know what the phase argument getting passed to phase methods is and why it's not the singleton?
     
    Thanks,
    Tudor
  4. Like
    getvictor got a reaction from girodias in UVM 1.2 Introduction and Code Examples   
    The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference
     
    This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM.
    The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide.
     
    The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher.
    uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon)  
    I hope you find it useful. Let me know what other topics you'd like to see.
     
    Note:
    The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
  5. Like
    getvictor reacted to fbochud in What's the matter with $cast()?   
    Cast cannot allocate for elements that are in my_packet and not in basePacket.
    In your example, P2 cannot be casted from P1 because the object is not created as a "my packet".
     
    To make it work, try (even though the scenario is a bit different):
     
        My_Packet P2 = new;
        BasePacket P1;

         initial begin
            P1 = P2;
            P1.printA;
            P1.printC;
            $cast(P2, P1);
            P2.printA;
            P2.printC;
        end
     
    cf http://www.edaplayground.com/s/934/1124
  6. Like
    getvictor got a reaction from lisakb1963 in UVM 1.2 Introduction and Code Examples   
    The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference
     
    This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM.
    The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide.
     
    The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher.
    uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon)  
    I hope you find it useful. Let me know what other topics you'd like to see.
     
    Note:
    The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
  7. Like
    getvictor got a reaction from agrawalyogesh04 in SystemC hands-on web-based simulations   
    Recently I added SystemC support to EDA Playground.
     
    Now it is possible to run SystemC simulations from your web browser (including viewing waves) without installing anything. Here is a SystemC counter design and testbench example
     
    1. Would this be useful for SystemC students and users (for sharing examples and best practices, prototyping, etc.)?
    2. Anyone interested in creating additional examples or web-based hands-on tutorials?
     
    For reference, here is a short YouTube intro: Run C++ and SystemC in Your Web Browser
  8. Like
    getvictor got a reaction from ljepson74 in Free systemverilog/uvm simulator for small amounts of code exists?   
    Update: EDA Playground now supports SystemVerilog and UVM. You can edit and simulate this simple UVM testbench: http://www.edaplayground.com/s/example/546
  9. Like
    getvictor reacted to uwes in How to call uvm_error from a static method?   
    hi,
     
    in static contexts you have to use the macro set with the postfix "_context". while the normal macros will invoke <this>.uvm_report_xyz() and therefore require a non static context the _context macros will invoke <context>.uvm_report_xyz(). messages emitted with the _context version can be used in static contexts and provide the same functionality as-if the non-context version would have been invoked in context.
     
    (an alternate use model for the _context macro version is to emit a message from a different place than what appears as the messages context. eg. you can print from within the driver BUT the context is showing as if the message was emitted by the agent)
     
    /uwe
  10. Like
    getvictor got a reaction from agrawalyogesh04 in Free systemverilog/uvm simulator for small amounts of code exists?   
    Update: EDA Playground now supports SystemVerilog and UVM. You can edit and simulate this simple UVM testbench: http://www.edaplayground.com/s/example/546
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