Jump to content

milind.shende5

Members
  • Content Count

    21
  • Joined

  • Last visited

  • Days Won

    1

Reputation Activity

  1. Like
    milind.shende5 got a reaction from Bicspoili in Error: CLK failed to set wave to 0 and Sampling id is greater than delay   
    Hi All, 
     
    while simulating A2D convertor, I got following problems. 
     
    Compilation: No Error
     
    running .exe file returns the following error message:
     
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------
    Warning: SystemC-AMS: Initialization for tracing of: CLK failed  set wave to 0   In file: sca_trace_object_data.cpp:136 In process: method_p_0 @ 0 s   Error: SystemC-AMS: Sample id (0) is greater than delay (0 while initializing port: A2D_dut.a2d.eoc In file: /home/4all/packages/systemc/2.2.0-sl4.5//include/scams/predefined_moc/tdf/sca_tdf_sc_out.h:418 In process: A2D_dut.a2d.sca_implementation_0.cluster_process_0 @ 0 s -----------------------------------------------------------------------------------------------------------------------------------------------------------------   In this regards, I have checked the complete code as well as the the files suggested in error message (/sca_tdf_sc_out.h:418), (sca_trace_object_data.cpp:136), but I did not get any clue.    my codes look like this:    //A2D.h   SCA_TDF_MODULE (a2d_nbit)   { //port declaration   sca_tdf::sca_in<double> a_in; // analog input pin     sca_tdf::sca_de::sca_in<sc_dt::sc_logic> start; //start signal   sca_tdf::sca_de::sca_in<bool> clk; //clock signal     sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin     sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > d_out; // digital output signal     a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-3, int bit_rng = 8):      a_in("a_in"), start("start"),clk("clk"), eoc("eoc"), d_out("d_out"), Vmax(Vmax_), delay(delay_), bit_range(bit_rng){}     void set_attribute()   {     set_timestep(1, sc_core::SC_MS);     eoc.set_delay(0);   }     void initialize()   {     eoc.initialize(sc_dt::SC_LOGIC_0);     start.initialize(sc_dt::SC_LOGIC_0);   }     void processing();     private:   double Vmax; // ADC maximum range   double delay; // ADC conversion time    int bit_range; //vector length of d_temp and d_out    };   //A2D_top_level.h   SC_MODULE (A2D_top_level) {   a2d_nbit a2d;    vtg_src input_vtg;   sc_core::sc_clock clk1;      void start_logic(){     while(true)       {           start.write(sc_dt::SC_LOGIC_0);           wait(20, sc_core::SC_MS);           start.write(sc_dt::SC_LOGIC_1);           wait(20, sc_core::SC_MS);           start.write(sc_dt::SC_LOGIC_0);           sc_core::sc_stop();       }   }      SC_CTOR(A2D_top_level)     : in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"),clk1("clk1",10, 0.5, true), start("start"), eoc("eoc")     {       input_vtg.out(in);              a2d.a_in(in);        a2d.start(start);       a2d.clk(clk1.signal());       a2d.eoc(eoc);       a2d.d_out(out);         SC_THREAD(start_logic);     }       public:       sca_tdf::sca_signal <double> in;     sc_core::sc_signal<sc_dt::sc_lv<8> > out;     sc_core::sc_signal<sc_dt::sc_logic> start;     sc_core::sc_signal<sc_dt::sc_logic> eoc;   };     //A2D_test.cpp   int sc_main(int argc, char* argv[]) {     A2D_top_level A2D_dut("A2D_dut");     sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("A2D.dat");     sca_util :: sca_trace(atfs, A2D_dut.a2d.clk, "CLK");   sca_util :: sca_trace(atfs, A2D_dut.start, "START");   sca_util :: sca_trace(atfs, A2D_dut.in, "INPUT");   sca_util :: sca_trace(atfs, A2D_dut.out, "OUTPUT");   sca_util :: sca_trace(atfs, A2D_dut.eoc, "EOC");     sc_start(1.5, SC_SEC);     sca_util :: sca_close_tabular_trace_file (atfs);     return 0;       }     could you please help in solving this problem....   regards,  Milind 
  2. Like
    milind.shende5 got a reaction from Annossyenudge in initialization problem with <sc_dt::sc_logic> port   
    Hello Geniuses, 
     
    in my ADC design, I have a output signal "eoc" (end of conversion), I declared it in port declaration like below
     
    sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc;
     
    In processing function, when I assign it a value '1' like below
     
    eoc = '1';
     
    I get following error message
     
    A2D.cpp: In member function ‘virtual void a2d_nbit::processing()’:
    A2D.cpp:50: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:50: error:   initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’   I also tried to initialize "eoc" in Initialize function like   eoc.initialize('1');   but then my compiler gives me another error as follows   A2D.cpp: In member function ‘virtual void a2d_nbit::initialize()’: A2D.cpp:28: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:28: error:   initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’   could you please suggest me how can initialize and assign sc_dt::sc_logic port ?   thanks in advance,    Milind.      
  3. Like
    milind.shende5 got a reaction from Annossyenudge in what is the best strategy to model A2D converter ? SC or SC-AMS   
    Hello All, 
    I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. 
     
    SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault 
     
    the models are as follows: 
     
    SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. 
     
    //error message:
    stage 1: start edge
    stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge ...... infinite loop    
    // SC_A2D.h
     
    #include<systemc.h>   enum adc_state {input, convert};   SC_MODULE(A2D_module) {   sc_in_clk clk;   sc_in_clk start;     sc_in<double> ain;      sc_out<sc_logic> eoc;   sc_out<sc_lv<8> > dout;     sc_signal <adc_state> status;     void conversion_logic();   //  void next_state_logic();     SC_CTOR(A2D_module)     {       SC_CTHREAD(conversion_logic, start.pos());     } };   //SC_A2D.cpp   #include <SC_A2D.h>   void A2D_module::conversion_logic() {   eoc = SC_LOGIC_0;   dout = "00000000";     double thresh, Vtemp;   sc_lv<8> dtemp;   int bit_cnt = 8;   status = input;     while(bit_cnt > 0)     {              switch (status){ cout << "begin !!!";         case input: if (start == 1)  {    cout << "stage 1: start edge" << endl;    thresh = 5.0;    Vtemp = ain;    eoc = SC_LOGIC_0;    status = convert;  } break;         case convert: if (clk == 1)  {    cout << "stage 2: clk edge" << endl;    thresh = thresh/2.0;        if (Vtemp > thresh)      { cout << "stage 3: Vtemp > thresh" << endl; dtemp[bit_cnt]= '1'; Vtemp = Vtemp- thresh;      }    else       { dtemp[bit_cnt]= '0';      }        if (bit_cnt > 0)      { cout << "stage 4: bit_cnt > 0" << endl; bit_cnt = bit_cnt - 1;      }    else      { cout << "last stage: conversion" << endl; dout = dtemp; status = input; wait(10, SC_US); eoc = SC_LOGIC_1;        }  } break;       } // end switch       } // end while          } // end method conversion_logic   -------------------------------------------------------------------------------------------------------------
     
    SC-AMS models: which gives segmentation fault
    // Error message:
    stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 2 : start edge stage 3: Convert Input stage 4: clk edge !!!  bit_cnt = 7 stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 3: Convert Input stage 4: clk edge !!! Segmentation fault    
    // A2D.h
     
    #include <systemc-ams> #include <systemc> #include <stdio.h> using namespace std;   //ref: VHDL-AMS Model of A2D converter given in System designer's guide to VHDL-AMS on page 287   SCA_TDF_MODULE (a2d_nbit)   { //port declaration   sca_tdf::sca_in<double> ain; // analog input pin     sca_tdf::sca_de::sca_in<bool> clk; //clock signal   sca_tdf::sca_de::sca_in<bool> start; //clock signal     sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin     sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > dout; //digitalized output         a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-6, int bit_range_ = 8, bool start_x_ = 0, bool clk_x_ = 0):     ain("ain"), start("start"),clk("clk"), eoc("eoc"), dout("dout"), Vmax(Vmax_), delay(delay_), bit_range(bit_range_), start_x(start_x_), clk_x(clk_x_){}     void set_attributes()   {     set_timestep(50, sc_core::SC_US);     eoc.set_delay(1);   }     void initialize()   {     eoc.initialize(sc_dt::SC_LOGIC_0);   }     void processing();     private:      double delay; // ADC conversion time    double Vmax;   int bit_range;    bool clk_x;   bool start_x;     };  
     
    // A2D.cpp
    void a2d_nbit :: processing()   {     //    double Vin = ain.read();     double thresh; //Threshold to test input voltage     double Vtemp; //snapshot of input voltage when conversion starts     sc_dt::sc_lv<8> dtemp; //temparary output data     enum state {input, convert};      int bit_cnt;     state status = input;       switch(status) // ref: systemC state machine example in SystemC user guide on page 171       {      case input :  cout << "stage 1: Read Input" << endl; if((start == true) && (start_x == false)) //if (start == true)  {    cout << "stage 2 : start edge" << endl;    bit_cnt = bit_range;    thresh = Vmax;    Vtemp = ain;    eoc = sc_dt::sc_logic('0');  }   case convert:  cout << "stage 3: Convert Input" << endl;  if ((clk == true)  && (clk_x == false))        //if (clk == true)      { cout << "stage 4: clk edge !!!" << endl; thresh = thresh/2.0;   if (Vtemp > thresh)  {    dtemp[bit_cnt]= '1';    Vtemp = Vtemp - thresh;  } else   {    dtemp[bit_cnt]= '0';  }   if (bit_cnt > 0)  {    bit_cnt = bit_cnt - 1;    cout << " bit_cnt = " << bit_cnt << endl;   } else   {    dout = dtemp;    eoc = sc_dt::sc_logic('1');       status = input;  } break;      }         default:  break;        } // end switch           start_x = start;     clk_x = clk;        }   ----------------------------------------------------------------------------------------------------------------   // voltage source: dummy_source.h    #include<systemc-ams> #include<systemc>   #include<iostream.h> #include<fstream.h>   using namespace std;   SCA_TDF_MODULE (dummy_src)   {   //  sca_tdf::sca_de::sca_out<double> output;    sca_tdf:: sca_out<double> output;   ifstream infile;   double val;     dummy_src(sc_core::sc_module_name): output("output"){}       void set_attributes()     {       set_timestep(50, sc_core::SC_US);       infile.open("datalog.txt");     }       void processing ()     {              if (infile >> val) { output.write(val); }        else { output.write(0.0); }            }       };   -------------------------------------------------------------------------------------------------------------   // top_level_entity : interface.h   #include<systemc-ams> #include<systemc>   #include<A2D.h> //#include<SC_A2D.h> #include<dummy_source.h>   using namespace std; using namespace sc_core;   SC_MODULE (interface2) {   // A2D_module a2d;   a2d_nbit a2d;   dummy_src input_vtg;   sc_core::sc_clock clk1;   sc_core::sc_clock start1;     SC_CTOR(interface2)     :in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"), clk1("clk1", 100, sc_core::SC_US, 0.5), start1("start1", 200, sc_core::SC_US, 0.5), eoc("eoc")     {       input_vtg.output(in);              a2d.ain(in);        a2d.start(start1.signal());       a2d.clk(clk1.signal());       a2d.eoc(eoc);       a2d.dout(out);       }       public:     //   sc_core::sc_signal <double> in;     sca_tdf::sca_signal<double> in;     sc_core::sc_signal<sc_dt::sc_lv<8> > out;     sc_core::sc_signal<sc_logic> eoc;   };     // top_level_entity: interface2.cpp   #include<systemc-ams.h> #include<systemc.h> #include<iomanip> #include<interface2.h>   int sc_main(int argc, char* argv[]) {     interface2 if2_dut("if2_dut");     sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("if2.dat");   sca_util :: sca_trace(atfs, if2_dut.clk1, "\tCLK");   sca_util :: sca_trace(atfs, if2_dut.start1, "\tSTART");   sca_util :: sca_trace(atfs, if2_dut.in, "\tINPUT");   sca_util :: sca_trace(atfs, if2_dut.out, "\tOUTPUT");   sca_util :: sca_trace(atfs, if2_dut.eoc, "\tEOC");   sc_start(400, SC_US);   sca_util :: sca_close_tabular_trace_file (atfs);   return 0; } -------------------  
  4. Like
    milind.shende5 got a reaction from Bicspoili in initialization problem with <sc_dt::sc_logic> port   
    Hello Geniuses, 
     
    in my ADC design, I have a output signal "eoc" (end of conversion), I declared it in port declaration like below
     
    sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc;
     
    In processing function, when I assign it a value '1' like below
     
    eoc = '1';
     
    I get following error message
     
    A2D.cpp: In member function ‘virtual void a2d_nbit::processing()’:
    A2D.cpp:50: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:50: error:   initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’   I also tried to initialize "eoc" in Initialize function like   eoc.initialize('1');   but then my compiler gives me another error as follows   A2D.cpp: In member function ‘virtual void a2d_nbit::initialize()’: A2D.cpp:28: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:28: error:   initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’   could you please suggest me how can initialize and assign sc_dt::sc_logic port ?   thanks in advance,    Milind.      
  5. Like
    milind.shende5 got a reaction from Bicspoili in what is the best strategy to model A2D converter ? SC or SC-AMS   
    Hello All, 
    I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. 
     
    SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault 
     
    the models are as follows: 
     
    SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. 
     
    //error message:
    stage 1: start edge
    stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge ...... infinite loop    
    // SC_A2D.h
     
    #include<systemc.h>   enum adc_state {input, convert};   SC_MODULE(A2D_module) {   sc_in_clk clk;   sc_in_clk start;     sc_in<double> ain;      sc_out<sc_logic> eoc;   sc_out<sc_lv<8> > dout;     sc_signal <adc_state> status;     void conversion_logic();   //  void next_state_logic();     SC_CTOR(A2D_module)     {       SC_CTHREAD(conversion_logic, start.pos());     } };   //SC_A2D.cpp   #include <SC_A2D.h>   void A2D_module::conversion_logic() {   eoc = SC_LOGIC_0;   dout = "00000000";     double thresh, Vtemp;   sc_lv<8> dtemp;   int bit_cnt = 8;   status = input;     while(bit_cnt > 0)     {              switch (status){ cout << "begin !!!";         case input: if (start == 1)  {    cout << "stage 1: start edge" << endl;    thresh = 5.0;    Vtemp = ain;    eoc = SC_LOGIC_0;    status = convert;  } break;         case convert: if (clk == 1)  {    cout << "stage 2: clk edge" << endl;    thresh = thresh/2.0;        if (Vtemp > thresh)      { cout << "stage 3: Vtemp > thresh" << endl; dtemp[bit_cnt]= '1'; Vtemp = Vtemp- thresh;      }    else       { dtemp[bit_cnt]= '0';      }        if (bit_cnt > 0)      { cout << "stage 4: bit_cnt > 0" << endl; bit_cnt = bit_cnt - 1;      }    else      { cout << "last stage: conversion" << endl; dout = dtemp; status = input; wait(10, SC_US); eoc = SC_LOGIC_1;        }  } break;       } // end switch       } // end while          } // end method conversion_logic   -------------------------------------------------------------------------------------------------------------
     
    SC-AMS models: which gives segmentation fault
    // Error message:
    stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 2 : start edge stage 3: Convert Input stage 4: clk edge !!!  bit_cnt = 7 stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 3: Convert Input stage 4: clk edge !!! Segmentation fault    
    // A2D.h
     
    #include <systemc-ams> #include <systemc> #include <stdio.h> using namespace std;   //ref: VHDL-AMS Model of A2D converter given in System designer's guide to VHDL-AMS on page 287   SCA_TDF_MODULE (a2d_nbit)   { //port declaration   sca_tdf::sca_in<double> ain; // analog input pin     sca_tdf::sca_de::sca_in<bool> clk; //clock signal   sca_tdf::sca_de::sca_in<bool> start; //clock signal     sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin     sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > dout; //digitalized output         a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-6, int bit_range_ = 8, bool start_x_ = 0, bool clk_x_ = 0):     ain("ain"), start("start"),clk("clk"), eoc("eoc"), dout("dout"), Vmax(Vmax_), delay(delay_), bit_range(bit_range_), start_x(start_x_), clk_x(clk_x_){}     void set_attributes()   {     set_timestep(50, sc_core::SC_US);     eoc.set_delay(1);   }     void initialize()   {     eoc.initialize(sc_dt::SC_LOGIC_0);   }     void processing();     private:      double delay; // ADC conversion time    double Vmax;   int bit_range;    bool clk_x;   bool start_x;     };  
     
    // A2D.cpp
    void a2d_nbit :: processing()   {     //    double Vin = ain.read();     double thresh; //Threshold to test input voltage     double Vtemp; //snapshot of input voltage when conversion starts     sc_dt::sc_lv<8> dtemp; //temparary output data     enum state {input, convert};      int bit_cnt;     state status = input;       switch(status) // ref: systemC state machine example in SystemC user guide on page 171       {      case input :  cout << "stage 1: Read Input" << endl; if((start == true) && (start_x == false)) //if (start == true)  {    cout << "stage 2 : start edge" << endl;    bit_cnt = bit_range;    thresh = Vmax;    Vtemp = ain;    eoc = sc_dt::sc_logic('0');  }   case convert:  cout << "stage 3: Convert Input" << endl;  if ((clk == true)  && (clk_x == false))        //if (clk == true)      { cout << "stage 4: clk edge !!!" << endl; thresh = thresh/2.0;   if (Vtemp > thresh)  {    dtemp[bit_cnt]= '1';    Vtemp = Vtemp - thresh;  } else   {    dtemp[bit_cnt]= '0';  }   if (bit_cnt > 0)  {    bit_cnt = bit_cnt - 1;    cout << " bit_cnt = " << bit_cnt << endl;   } else   {    dout = dtemp;    eoc = sc_dt::sc_logic('1');       status = input;  } break;      }         default:  break;        } // end switch           start_x = start;     clk_x = clk;        }   ----------------------------------------------------------------------------------------------------------------   // voltage source: dummy_source.h    #include<systemc-ams> #include<systemc>   #include<iostream.h> #include<fstream.h>   using namespace std;   SCA_TDF_MODULE (dummy_src)   {   //  sca_tdf::sca_de::sca_out<double> output;    sca_tdf:: sca_out<double> output;   ifstream infile;   double val;     dummy_src(sc_core::sc_module_name): output("output"){}       void set_attributes()     {       set_timestep(50, sc_core::SC_US);       infile.open("datalog.txt");     }       void processing ()     {              if (infile >> val) { output.write(val); }        else { output.write(0.0); }            }       };   -------------------------------------------------------------------------------------------------------------   // top_level_entity : interface.h   #include<systemc-ams> #include<systemc>   #include<A2D.h> //#include<SC_A2D.h> #include<dummy_source.h>   using namespace std; using namespace sc_core;   SC_MODULE (interface2) {   // A2D_module a2d;   a2d_nbit a2d;   dummy_src input_vtg;   sc_core::sc_clock clk1;   sc_core::sc_clock start1;     SC_CTOR(interface2)     :in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"), clk1("clk1", 100, sc_core::SC_US, 0.5), start1("start1", 200, sc_core::SC_US, 0.5), eoc("eoc")     {       input_vtg.output(in);              a2d.ain(in);        a2d.start(start1.signal());       a2d.clk(clk1.signal());       a2d.eoc(eoc);       a2d.dout(out);       }       public:     //   sc_core::sc_signal <double> in;     sca_tdf::sca_signal<double> in;     sc_core::sc_signal<sc_dt::sc_lv<8> > out;     sc_core::sc_signal<sc_logic> eoc;   };     // top_level_entity: interface2.cpp   #include<systemc-ams.h> #include<systemc.h> #include<iomanip> #include<interface2.h>   int sc_main(int argc, char* argv[]) {     interface2 if2_dut("if2_dut");     sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("if2.dat");   sca_util :: sca_trace(atfs, if2_dut.clk1, "\tCLK");   sca_util :: sca_trace(atfs, if2_dut.start1, "\tSTART");   sca_util :: sca_trace(atfs, if2_dut.in, "\tINPUT");   sca_util :: sca_trace(atfs, if2_dut.out, "\tOUTPUT");   sca_util :: sca_trace(atfs, if2_dut.eoc, "\tEOC");   sc_start(400, SC_US);   sca_util :: sca_close_tabular_trace_file (atfs);   return 0; } -------------------  
  6. Like
    milind.shende5 reacted to karandeep963 in what is default time unit in systemC   
    As per my understanding:
     
     
    As per your declaration for clock object sc_clock ck1("ck1", 20,SC_NS,  0.5, 0,SC_NS,  true); the first edge will occur at 0 not at 2 time units.
     
    Yes , its correct.
     
     
    1st  Option: will produce the clock of time period 20 micro seconds,
    2nd Options: I am not sure that whether it should work without specifying the time unit for clock period. Ideally , it should give an syntax error i guess for missing the time unit argument for clock period.
     
    Correct me if I am wrong.
     
    ----
    Karandeep
  7. Like
    milind.shende5 reacted to apfitch in what is default time unit in systemC   
    That is an obsolete document, I do not recommend using it. It was never a standard.
     
    Use the IEEE 1666-2011 standard. If you read that standard, there is a list of deprecated features, including on page 583 the information that default time unit is deprecated.
     
    n) Default time units and all the associated functions and constructors, including:
    1) Function sc_simulation_time
    2) Function sc_set_default_time_unit
    3) Function sc_get_default_time_unit
    4) Function sc_start(double)
    5) Constructor sc_clock(const char*, double, double, double, bool)
     
     
    No, there is no default time unit. You are quoting an obsolete document which was never a standard.
     
    However there is a default constructor for sc_clock, which sets the default clock *period* to 1 ns. So if you wrote
     
    sc_clock clock;  // name is "clock_0", period 1, SC_NS, posedge_first true, delay to first edge 0, SC_NS
     
    See the LRM description of sc_clock, p149ff.
     
    There is a default time *resolution* of 1 ps. What that means is if you say
     
    wait(1.0001, SC_NS);
     
    you will lose the fractional part of the time delay as it is less than 1 ps. You can change the *resolution* using sc_set_time_resolution() (see page 102).
     
     
    Yes that works.
     
    No that doesn't work. You still have to use 20, SC_US with SystemC 2.1, 2.2, 2.3 (LRM 1666-2005 1666-2011).
     
    There is no default time unit.
     
    Don't mix up the time resolution (the minimum representable time value) and default time unit (a deprecated feature of SystemC before it was standardised).
     
    regards
    Alan
     
  8. Like
    milind.shende5 reacted to apfitch in what is default time unit in systemC   
    There is no default time unit. You should always specify the time unit, e.g.
     
    wait(1, SC_NS);
     
    regards
    Alan
     
    P.S. If you really meant time resolution, see section 5.11.3 of IEEE 1666-2011
  9. Like
    milind.shende5 reacted to karandeep963 in what is default time unit in systemC   
    sc_set_time_resolution sets the time resolution.
     
    The function sc_get_time_resolution shall return the time resolution.
     
    5.11.3 Time resolution @ page no. 102 IEEE Std 1666-2011
    IEEE Standard for Standard SystemC® Language Reference Manual   -- Karandeep
  10. Like
    milind.shende5 reacted to dakupoto in what is the best strategy to model A2D converter ? SC or SC-AMS   
    Hello Sir,
    There is no need to use a while loop, except
    perhaps in some special case, in the TDF
    framework. The TDF framework offers a set of
    methods that can be overriden and if used
    correctly/wisely will remove the need for a
    while loop.
    In the 'set_attributes()' method, one can
    use the built-in 'set_timestep()' method to
    set when data is read in from an input port,
    or read out to an output port. So at tick or
    sub-interval of the total simulation time,
    data is read in/out as specified.
    But this is what is done in pure SystemC as
    well, for a SC_THREAD or SC_CTHREAD. There
    A sensitivity list defines the triggering
    event, often a clock, at which the thread
    has to respond. So the thread is set up as
    an infinite loop, that 'waits' for a triggering
    event.
    So, SystemC-AMS provides a cleaner design
    that does not force the designer to explicitly
    track the triggering event. In the 'processing'
    method, the actual processing is done.
    Hope that helps.
      
  11. Like
    milind.shende5 reacted to dakupoto in Cannot find commonsrcs.h and gendatatrace.h files in systemc-ams package   
    I am very sorry for your troubles. Actually the publisher Springer has a link from their own
    Web site to a FTP site from where the source code tarball might be downloaded, PROVIDED
    you buy from Springer itself. Amazon has not yet included a FTP URL. Currently, Amazon
    and Springer are trying to work out a solution. So please wait, something will be worked out.
    Both commonsrcs.h and gendatatrace.h contain utility code.
    commonsrcs.h provides utility classes to create some signal sources as square wave, triangle
    wave.
    gendatatrace.h provides utility classes to format output data for plotting with Gnuplot.
    Please supply me an email at dakupoto@gmail.com and I can email the two files to you.
  12. Like
  13. Like
    milind.shende5 reacted to Philipp A Hartmann in can we input a stimuli from a text file ?   
    The function to set attributes for TDF MoC elaboration is called set_attributes() (plural form). You should be able to find such an error quite quickly by either adding simple debugging messages ("printf-debugging") or by using a proper debugger.
     
    Greetings from Oldenburg,
      Philipp
  14. Like
    milind.shende5 reacted to maehne in can we input a stimuli from a text file ?   
    Hello Milind,
     
    your dummy_src won't work as you're mixing in it DE and TDF semantics! In the context of TDF module, you are not at all allowed to call sc_core::wait()! Instead of the while loop in your processing() callback, use something like:
     
    if (infile >> val) {
      output.write(val);
    } else {
      output.write(0.0);
    }
     
    The time distance between the output samples is defined by the module timestep, which you specified in set_attributes().
     
    Regards, Torsten
  15. Like
    milind.shende5 reacted to maehne in Error: CLK failed to set wave to 0 and Sampling id is greater than delay   
    Dear Milind,
     
    SystemC AMS 1.0 doesn't offer a possibility to initialize the initial value of a DE signal of type sc_core::sc_signal<T> through a TDF converter output port of type sca_tdf::sca_de::sca_out<T>. This missing functionality has been added in SystemC AMS 2.0 with the sca_tdf::sca_de::sca_out<T>::initialize_de_signal() member function. In SystemC AMS 1.0, you will have to initialize the sc_core::sc_signal<T> directly from your top cell using the channels initialize() member function.
     
    Regarding the your sc_clock initialization problem, you're are using a deprecated pre-SystemC 2.0 version of the sc_clock constructor, which still accepts an integer argument without an associated time unit and then interprets that integer value as a multiple of the sc_core::sc_set_time_resolution(). Don't do this! Instead, replace:
     
    clk1("clk1",10, 0.5, true)
     
    with 
     
    clk1("clk1",10, sc_core::SC_MS, 0.5)
     
    Please check clause 6.7 on sc_clock in IEEE Std 1666-2005 for more information on the sc_clock's constructors.
     
    An sc_clock has no knowledge at all of the time step, you assign to a TDF cluster. Indeed, SystemC has no particular knowledge about semantics of SystemC AMS. SystemC AMS has been just defined in a way that it's enhancements can be implemented and executed within the constraints and semantics defined by the SystemC standard. SystemC AMS thus doesn't need to modify the SystemC simulation kernel.
     
    That said, please be aware of the limitations of the DE<->TDF synchronization semantics, which are defined the LRM and also discussed more clearly in the SystemC AMS User's Guide. A TDF cluster is always executed at delta cycle 0 of a given SystemC time and will sample the value of a DE signal, which is valid at that time. Any value written to a DE signal via a TDF converter output port,  will become valid for the DE side at delta cycle 1.
     
    I also have some concerns regarding your A2D_top_level::start_logic() thread: You probably don't want to call sc_stop() from within it, as you will force the end of the simulation after just 40 ms, whereas you initially started the simulation for 1.5 s. Instead, just wait indefinitely long using wait() without any arguments.
     
    Regards, Torsten
  16. Like
    milind.shende5 reacted to maehne in Error: CLK failed to set wave to 0 and Sampling id is greater than delay   
    Hello Milind,
     
    The error message regarding the delay is caused by your calls to sca_tdf::sca_de::sca_out<T>.initialize() in the a2d_nbit::initialize() callback. By simply removing the two initialize() callbacks in this callback, the error will disappear. The reason is the semantical difference between initialize() of a TDF (converter) port and that of a DE port. The initialize() of sc_core::sc_in<T>, sc_core::sc_out<T>, and sc_core::sc_inout<T> will set the initial value of the sc_core::sc_signal<T> bound to the port. The initialize() of sca_tdf::sca_in<T>, sca_tdf::sca_out<T>, sca_tdf::sca_de::sca_in<T>, sca_tdf::sca_de::sca_out<T> will initialize the delay samples of the port. By default, a TDF port has a delay of zero! Therefore, you are not allowed to call initialize on these kind of ports in the context of the TDF module's initialize() callback. Once you specify a sample delay of n samples on a TDF ports in the module's set_attributes() callback, you can initialize the delay samples with id 0 to n-1 using initialize(val, id).
     
    For more information, have a look in the SystemC AMS User's Guide and the SystemC and SystemC AMS LRMs.
     
    Regards, Torsten
  17. Like
    milind.shende5 reacted to maehne in internal signal error   
    The converter ports sca_tdf::sca_de::sca_in<T> and sca_tdf::sca_de::sca_out<T> have to be bound to DE signals of type sc_core::sc_signal<T> (cf. to Figure 2.20 in section 2.3.3 in the SystemC AMS User's Guide).
  18. Like
    milind.shende5 reacted to Philipp A Hartmann in initialization problem with <sc_dt::sc_logic> port   
    The sc_logic constructor taking a char is marked as explicit.  Therefore, you can't pass a char to functions expecting an sc_logic (e.g. initialize).
     
    You can either explicitly create (pun intended) an sc_logic from a char, or use the predefined sc_logic constants for assignments and parameter passing:
    sc_logic a; a = sc_logic('1'); eoc.initialize( SC_LOGIC_0 ); // SC_LOGIC_1, SC_LOGIC_X, SC_LOGIC_Z Greetings from Oldenburg,
      Philipp
×
×
  • Create New...