kansagaratushar

HI, It indicates TLM port declaration, Here "uvm_blocking_get_port" is TLM and used to communicate with other block. "Simple_trans" is data type of communication. get_port is substantiation, For more Details Refer http://testbench.in/UT_13_UVM_TLM_1.html

class my_transaction extends uvm_sequence_item; .... int a; int b; int c; .... endclass class my_sequence extends uvm_sequence#(..) .... my_transaction tx; ... `uvm_do_with(tx,{tx.a==1;tx.b==1;tx.c==1;}) .... endclass class my_complex sequence extends uvm_sequence#(...) my_sequence seq; .. .. `uvm_do_with(seq,{seq.a==0;seq.b==0;seq.c==0;}) // This Doesn't work........How can I change value of a,b,c in this situation?