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Everything posted by wszhong631

  1. hi, In uvm_phase file of uvm1.2, I understand that before_phase.m_successors.delete(after_phase) which is the 978th line code of add method should be 'before_phase.m_predecessors.delete(after_phase) ' , that is right ? 965 // IN BETWEEN 'BEFORE' and 'AFTER' PHASES 966 else if (before_phase != null && after_phase != null) begin 967 if (!after_phase.is_before(before_phase)) begin 968 `uvm_fatal("PH_ADD_PHASE",{"Phase '",before_phase.get_name(), 969 "' is not before phase '",after_phase.get_name(),"'"}) 970 end 971 // before
  2. you must compile questasim_uvm_package.sv ,and vsim -uvmcontrol=all ,then add sequences to wave using UVM-Aware Debug windows, also,may add monitor transaction to wave using transaction record method , the version of mentor tools should 10.2b above. ,ple reference questa SIM user Mannal.
  3. Hi,I have such a question https://verificationacademy.com/forums/uvm/how-use-soft-constraint who can help me ? thanks /wszhong
  4. Hi! often,in uvm test, host controller write or read registers through addresses,so, I define some parameter in a package using `define in replace of register address. then , import the package into my test lib package, compile in order , test lib package is compiled lastly, but when compling code ,report macro address can't find? How to using package rightly in UVM? Large projects may have many packages with complex interdependencies,How to using it rightly ? thanks. /wszhong
  5. hi, I will be ready to build one layer protocol testbench, top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that 1) trans_item is toper level sequence item(transaction layer item); 2) link_item is lower level sequence item(ie,link layer item); patial code as follows: class trans_item extends uvm_sequence_item; rand bit [31:0] mess_data[]; rand bit [15:0] mess_len; constraint C_mess{ soft mess_data.size()==mess_len;
  6. sorry,payloadseqment is a mis-spelling error when written this question. in sequence_item.svh, rand [7:0] payloadsegment[]; // payloadsegment that payload of some packets https://verificationacademy.com/forums/uvm/why-payloadsegment0-not-legal-c-identifier-namebut-payloadseqment0 Dave_59 says as follows "This warning is generated by Questa's built-in UVM-aware debug facilities. In order to use the debugging tools, the UVM created paths need the ability to be parsed by the command line. All vendor tools have this problem. You can ignore these warnings if you do not plan to us
  7. in order to watch UVM_details windows in questasim10.2c/10.2b,vlog option + questa_uvm_pkg options. Makefile as follows: questa_uvm_pkg=/app/mentor/questasim_10.2c/questasim/verilog_src/ vlog +incdir+$(uvm_home)/src $(uvm_home)/src/uvm.sv \ +incdir+$(questa_uvm_pkg) $(questa_uvm_pkg)/questa_uvm_pkg.sv ............... under of simulation,report warning as follows: questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_recorder.svh(364) @4080840000: reporter [iLLEGALNAME] 'payloadsegment[0]' is not a legal c identifier name.change to questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_re
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