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Viewing Profile: SumitK
Viewing Topic: uvm_reg_bit_bash_seq usage..
1 minute ago
Viewing Topic: uvm_mem get_default_map problem
3 minutes ago
Viewing Topic: SC_METHOD and next_trigger() diagnostics
Viewing Topic: Top level parameters in composite IP with CCI
5 minutes ago
Viewing Forums Index
7 minutes ago
Viewing Topic: UVM 1.2 Introduction and Code Examples
8 minutes ago
Viewing Topic: problem about variable part select in SystemVerilog
10 minutes ago
Viewing Topic: Passing information between sequence and test
Viewing Topic: Semaphore/uvm port
Viewing Topic: Unique array elements without rand or randc
11 minutes ago
Viewing Topic: how to pass a cmdline argument file when run simulation
12 minutes ago
Viewing File: vim syntax highlighting file for Verilog, Systemverilog and UVM
13 minutes ago
14 minutes ago
Viewing Topic: wait for 'delay' cycles
15 minutes ago
Viewing Topic: switch case
Viewing Topic: Use of intersection in cross coverpoints
Viewing Topic: Can't randomize members of class derived from uvm_sequence
16 minutes ago
Viewing Topic: std::randomize( vs. randomize( vs. this.randomize( and scope
17 minutes ago
Viewing Topic: SwitchToFiber called on NULL-pointer
