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  1. Managed to run SystemC on new Apple M1 silicon, following are the steps 1. modify configure file, add the following code highlighted in red # check CPU architecture case ${target_cpu} in #( x86_64|amd64) : TARGET_ARCH="${TARGET_ARCH}64" CPU_ARCH="x86_64" QT_ARCH="x86_64" ;; #( x*86|i*86) : CPU_ARCH="i386" QT_ARCH="iX86" ;; #( powerpc64) : TARGET_ARCH="${TARGET_ARCH}ppc64" CPU_ARCH="ppc64" QT_ARCH="pthreads" ;; #(
    2 points
  2. Matthias Jung

    C++20 Co-routines

    For my SystemC-Lecture, I wrote a simple DES simulator to reduce to the minimal mechanisms that are required to understand the DES concept. (https://github.com/myzinsky/des/tree/main/sw). For that I used C++20 co-routines for the 'processes'. Therefore, I was wondering if somebody has considered these co-routines also as co-routines for SystemC, instead of qt, pthreads or fibers?
    2 points
  3. Actually the usual bus protocols allow to send larger number of requests and the interconnect is allowed to answer them 'out of order' (e.g. AMBA AXI or CHI). But you are free to define you onw protocol and its own rules. The LRM states exactly how to do this. One example can be found at https://github.com/Arteris-IP/tlm2-interfaces which defines the extensions and phases for the AXI/ACE and the CHI protocol.
    2 points
  4. Hello @berry_runner, Regarding a dedicated training look here: https://www.doulos.com/training/ But as a starter in this, I would recommend getting to know following in no particular order: C++11/14/17: Useful for writing concise and clean code. SystemC from Ground Up 2nd Edition by @David Black. https://github.com/dcblack/SCFTGU_BOOK/ Look into the examples directory in SystemC sources. https://github.com/accellera-official/systemc/tree/master/examples Look into publicly released projects on Github: https://github.com/topics/systemc
    2 points
  5. Just to add 2 cents to @David Black proposal: If the instantiation is exepensive you could fork() (https://en.wikipedia.org/wiki/Fork_(system_call)) your programm after instantiating the design. Basically you create a new OS process as copy of the current one and here you can continue the simulation. But in essence it is the same approach as David described.
    2 points
  6. The primary reason is that the SystemC Proof-of-Concept (PoC) implementation uses some global data structures, which get constructed during elaboration, which are not fully cleaned up when sc_stop() is called. These data structures are only freed by the OS when the application quits. There have been some efforts improve the PoC implementation in this area, but these are currently stalled. Unfortunately, partially due to bad code examples, bad habits, and laziness, many SystemC models also not cleanly deallocate their dynamically allocated resources, as they still use manual resource allocation
    2 points
  7. You cannot bind an output port to an input port. Ultimately each port must bind to a signal either hierarchically (this is where port to port binding can is used) or directly. So you need to define signal for each of the test_module output ports and bind the sc_out and sc_inout ports to it. 2 remarks: you should use sc_in instead of sc_inout to indicate the purpose clearly sc_out is just a child of sc_inout to reduce the number of output ports (and hence signal) you might want to group signals logically belonging together into structs. Those can be used as data typs of si
    2 points
  8. Port requires a pointer towards the object containing implementations of methods specified in the interface. Export provides the very pointer that port needs. Port goes from caller towards callee. Export goes from callee towards caller. Pseudo-graphically: // +----------------------------------------------------------------------------------+ // |struct Top : sc_module { | // | | // | initiator.p1.bind( target.x1 );
    2 points
  9. I had a look onto your code and it has several flaws: your condion variable not protected against spurious and lost wakeups you use one global condition variable for all threads. This is bad design... your simulation runs out of events. Since the SC kernel does not see any events during the start of your thread(s), it simply shuts down the simulation. So before your thread is alive there is no simulation at all diamond problem with multiple inheritance: ThreadSafeEvent inherits of sc_prim_channel and ThreadSafeEventIf where both inherit of sc_interface. So at least Thre
    1 point
  10. maehne

    (max. 20 printed)

    The cause for the empty VCD file is probably due that you call at the end the wrong closing function sca_close_tabular_trace_file(tfp_vcd) instead of the correct one sca_close_vcd_trace_file(tfp_vcd). As Martin Barnasconi wrote, VCD files are not well suited for tracing TDF, LSF, and ELN signals, because these signals tend to change at each time step. VCD is best suited for discrete event signals.
    1 point
  11. David is correct, another program having issues with Quickthreads is valgrind. With Quickthreads SystemC threads actually all live in a single pthread. When a SystemC thread yields to another one the stack is changed from one piece of storage to another in a discontinuous manner. The stack for that single pthread that SystemC is living ends up being discontinuous. With pthreads enabled each SystemC thread is in its own pthread and those stacks are continuous.
    1 point
  12. You need to specify the timestep to at least one TDF module or TDF port, using method set_timestep. In a TDF module this method should be called in the callback set_attributes. See section 2.3.1 (Discrete-time modeling) and Example 2.11 in the SystemC-AMS User's Guide.
    1 point
  13. uvm_config_db is simply a facade pattern on top of the uvm_resource_db. As mentioned above, most recommend avoiding direct use of the resource db because the config db adds more consistency to its use.
    1 point
  14. The simple answer is that SystemC does not know how to trace std::string, and much less and array of std::string. First, std::string is a dynamically variable array of characters, which will perplex waveform viewing because you need a fixed number of signals to display. Changing to a fixed std::array<char,10> would help. You would still need to write an overload something like: template<int depth> void sc_trace( sc_trace_file* tf, const std::array<char,depth>& A, const std::string& name ) { // Code to trace individual char's for(int i=0; i<depth;
    1 point
  15. 1. uvm_resource_db is a datbase which is used as basis for uvm_config_db. uvm_config_db is adding more flexibility to uvm_resource_db. 2. You should never use uvm_resource_db 3. Is obsolete because of 2.
    1 point
  16. If you can avoid global variables at all cost. The will bite you more you think. If you need to have static global variables (e.g. for loggers or memory managers) use the Meyers-SIngleton. Those will be initialized upone first use which usually gives you some control over the live cycle. Another example can be found here: https://github.com/Minres/SystemC-Components/blob/master/incl/tlm/tlm_mm.h
    1 point
  17. You'll have to create internal (i.e., private) signals for each member of the bundled class, which you need to connect to sub-blocks. Then, you have to register a SC_METHOD or SC_THREAD, which is sensitive to changes of the bundled input. The method/thread can then assign the correct new values to the internal signals based on the changed bundled input.
    1 point
  18. Not sure if this topic is active. Here is some feedback. 1. Decouple the datatypes library from other core SystemC libraries. In other words it should be a light stand-alone library of its own. 2. Single unified bit vector library for all widths (like ac_int<W>). However having the range function for behavioral modeling (not synthesis) is also very useful. Currently we use the following c++-11 feature: /*----------------------------------------------------------------*/ // This uses a neat template alias trick introduced in C++-11 // to hide the underlying type of either a
    1 point
  19. To fix the issue, you can simply create a symbolic link lib-linux64, which points to lib, inside your SystemC installation directory /home/computation/Desktop/systemc-2.3.3-install using: cd /home/computation/Desktop/systemc-2.3.3-install ln -s lib lib-linux64 The experimental CMake-based build system distributed with SystemC provides to this end the setting INSTALL_LIB_TARGET_ARCH_SYMLINK. If enabled (default is OFF), the symlink is automatically created during installation of the SystemC library. Ideally, all SystemC-related libraries would provide a CMake-based build system, which wo
    1 point
  20. @plafrattTLM2 is built to allow any protocols you like. The "base protocol" was deemed sufficient for most needs; however, TLM2 was designed specifically to allow alternatives. Furthermore, the standard provides mechanisms to keep the cost of adapters/bridges between protocols simulation efficient. [Plug - ignore if you like] The Doulos course on TLM 2.0 <https://www.doulos.com/training/systemc-tlm-20/systemc-modeling-using-tlm-20-online/> investigates the base protocol and then builds up to a module describing custom protocols.
    1 point
  21. Paul Floyd

    A few Valgrind issues

    Here is a full analysis of the first problem, and a proposed patch. Here's what I saw running the executable under Valgrind via the GDB server (this is required to execute the mo(nitor) command). 257 result_p->digit = (sc_digit*)sc_core::sc_temp_heap.allocate( 258 sizeof(sc_digit)*result_p->ndigits ); 259 #if defined(_MSC_VER) 260 // workaround spurious initialisation issue on MS Visual C++ 261 memset( result_p->digit, 0, sizeof(sc_digit)*result_p->ndigits ); 2
    1 point
  22. Paul Floyd

    A few Valgrind issues

    More details on the other two issues systemc/misc/user_guide/chpt4.4 ==165605== Invalid write of size 8 ==165605== at 0x49FACA6: sc_core::sc_object::orphan_child_objects() (sc_object.cpp:336) ==165605== by 0x49F5D46: sc_core::sc_module::~sc_module() (sc_module.cpp:273) ==165605== by 0x406CC3: stage1_2::~stage1_2() (stage1_2.h:43) ==165605== by 0x406B95: pipeline::~pipeline() (pipeline.h:43) ==165605== by 0x406C38: pipeline::~pipeline() (pipeline.h:43) ==165605== by 0x49F5343: sc_core::sc_module_dynalloc_list::~sc_module_dynalloc_list() (sc_module.cpp
    1 point
  23. Paul Floyd

    A few Valgrind issues

    So, for the 1st item that I've looked at the most, I reproduced this on Fedora 33 amd64 with the default GCC [gcc (GCC) 10.2.1 20201125 (Red Hat 10.2.1-9)]. The SystemC library is the latest from github and regressions systemc-regressions-2.3.3 from Accellera. Valgrind is the latest release, 3.16.1. I also reproduced the same issue on FreeBSD 12.2 with the default clang (10 I believe). That was with my own build of Valgrind, a bit more recent than 3.16.1 but no significant differences on amd64. The 2nd and 3rd items I also saw on FreeBSD and I'm rerunning the full set of tests on F
    1 point
  24. This part is wrong: for ( int i=0; i<N ; i++){ for ( int j=0; j<NB_elements_trans ; j++){ i_adder = new adder("i_adder"); i_adder->in[j](sig_data[i][j]); } i_adder->out(sig_add); } You create N x NB_elements_trans i_adder elements and on each of them you only connect 1 of 4 in ports. I guess you mean: for ( int i=0; i<N ; i++){ i_adder = new adder("i_adder"); for ( int j=0; j<NB_elements_trans ; j++){ i_adder->in[j](sig_data[i][j]); } i_adder->out(sig_add); } A few remarks: you create a memo
    1 point
  25. Hello @Beginner_KOR, You can follow a similar discussion here: Hope this helps. Regards, Ameya Vikram Singh
    1 point
  26. Hello @Issraa, Can you share the directory listing(ls -al) for the mentioned path below: ls -al /home/israa/systemc-2.3.3/ # or more appropriately ls -al $SYSTEMC_HOME Regards, Ameya Vikram Singh
    1 point
  27. In the constructor list you would provide a creator function. This is a functor(a function pointer, a std::function object, a Functor classinstance, a lambda function, ...) which accepts a char const* and a size_type and returns a constructed object. In your case it would look like (C++11): class example: public sc_core::sc_module { public: sc_core::sc_vector<sc_core::sc_fifo<unsigned>> fifos; example(sc_core::sc_module_name nm, unsigned outputs) : sc_core::sc_module(nm) , fifos("fifos", outputs, [](char const* name, unsigned i)->sc_core::sc_fifo<unsigned&g
    1 point
  28. SystemC FIFO's represent hardware and as such may only be created during construction of a model. After elaboration closes, you are not allowed to add more fifos. None of your code examples above are complete, so it is fairly hard to give you a complete answer. Perhaps you could put your design on https://edaplayground.com and share a link with us. For details on phases of SystemC (e.g. elaboration) see IEEE-1666-2011.pdf, which you can obtain through Accellera.org.
    1 point
  29. This is not really a memory leak, but a very bad „model“ for the current implementation. I wonder if you saw any such scenario in a real model? „Canceled“ notifications like in your case will still be kept in the kernel‘s internal data structures until the notification time is reached (1ms in your case). You would pile up 999,999,999 of these canceled notifications until they are „deallocated“, each of them taking entries in the event queue and 16 bytes for the notification itself. Which is a lot of memory. I wrote „deallocated“ in quotes, because sc_event_timed uses a very simple m
    1 point
  30. sc_fifo<T> is a channel representing hardware FIFO behavior. sc_fifo_in<T> is a specialized port used to access an sc_fifo channel. Almost identical to sc_port<sc_fifo_in_if<T>> Suggestion: Read the freely available SystemC standards document (IEEE-1666-2011) or obtain a book on SystemC. It's all very clear there.
    1 point
  31. SCV does not contain an the respective overloads for scv_introspection and _scv_distribution. Therefore there is afaik no way to simply randomize a vector. As a workaround you might use the randomization for plain C-style arrays.
    1 point
  32. Hi all, So, I'll start by stating the problem. The problem is that it is not possible to use Quickthreads on 64 bit Windows. Basically, for sake of consistency with other platforms as well as 32 bit Windows, I need to be able to use Quickthreads as well. So, before I begin I have a question: What is the out of the box choice for SystemC threads on Windows platforms both 32 bit and 64 bit? As far as I understand from the configure script, WinFibers is what will be used for Windows if MinGW is being used: # use WinFiber on MinGW platforms
    1 point
  33. You cannot call sc_main directly from main(). main() comes with the SystemC reference implementation (SystemC simulator) and initailizes the simulation kernel. You miss that in your main function, you migh tlook it up at https://github.com/accellera-official/systemc/blob/master/src/sysc/kernel/sc_main.cpp and https://github.com/accellera-official/systemc/blob/master/src/sysc/kernel/sc_main_main.cpp Despite that, you cannot call your sc_main twice. The simulation kernel in the reference implementation is not re-entrant. Thus the LRM states in section 4.3.4.2 Function sc_start: in t
    1 point
  34. David Black

    About AT

    TLM (Transaction Level Modeling) is focused on communication (interconnection) of SystemC models. So your question is slightly irrelevant. From what you indicate, I would say that AT modeling style would accomplish what you are interested in. Sockets are an almost essential aspect of TLM as they simplify modeling and can provide information about the transaction. As to what metrics you can get, that is up to you. SystemC is not a prepacked set of subroutines, nor is it a narrowly focused on one type of analysis. SystemC is a methodology using C++ to model any variety of ideas using an ev
    1 point
  35. David Black

    About AT

    Approximately-Timed (AT) models provide decent timing accuracy for modeling purposes. Common use cases include architectural analysis (cost vs performance). AT models are used to understand the effects of interconnect and bus protocols on overall performance. Loosely-Timed (LT) models provide for simulation performance (i.e. fast), but often use techniques that sacrifice modeled timing accuracy. The intent is for use in software development on virtual platforms. Techniques used include Temporal De-coupling coupled a notion of a Quantum, and Direct Memory Interface. LT models usually try t
    1 point
  36. Silly me, I was quite mistaken in my simple solution (and it only took me a few minutes after posting to realize it); however, this exercise reminded me of a 2011 feature: reset. This works for SC_METHOD processes, but is inconvenient for SC_THREADs. I enjoyed working the puzzle. You can see a full working example here: https://www.edaplayground.com/x/39QM Outline: When registering your SC_METHOD process capture the process handle and specify dont_initialize(). At the start of your method implementation, check for the trigger state of reset_event and return immediately if
    1 point
  37. UVM-SystemC 1.0-beta3 was released for public review. Download available at https://www.accellera.org/downloads/drafts-review. Notable changes since 1.0-beta2: Register API Bugfixes & SystemC 2.3.3 support Ubus example Automatic objection mechanism
    1 point
  38. AFAICS you don't increment the index i in the while loop. But your code is way to complex.: std::ifstream ifs("TEXT.txt"); if(ifs.is_open()){ int buf = 0; for (int i = 0; i < MEM_DEPTH; i++) { ifs >> buf; buff_1[i]=buf } } ifs.close(); should replace everything from fopen() until fclose(). And you should avoid using macros, they will bite you. '#define MEM_DEPTH 20' should become 'const size_t MEM_DEPTH=20;'.
    1 point
  39. UVM is all about reuse. Reuse has several different aspects: Reuse of an engineers knowledge -- those experienced with UVM can usually jump onto an existing or new UVM project with very little ramp time. I have seen some verification environments using their own methodology that literally took months for new engineers to come up to speed on. Mind you misuse of UVM can lead to the same conclusion if you don't stay within the standard itself. Reuse of verification components -- means you can reuse a UVM environment without editing a single line of code provided by that environment. T
    1 point
  40. module who_changed_first(input a, b, start); always @(posedge start) begin byte changed; WATCHERS: fork @a changed = "a"; @b changed = "b"; join_any disable WATCHERS; //< prevent others from overwriting case (changed) "a": work_1; "b": work_2; endcase end Assumes SystemVerilog. If Verilog you will need to add . See https://edaplayground.com/x/2NXz for example code.
    1 point
  41. Dave5144

    Guide/Help for Beginners

    I got the examples to build under VS2019 by modifying the visual studio install to use VS 2015 build tools. It's a box you can click under the C++ install options. I also had to delete the previously downloaded systemC folders then re-download them. Build the VS2010 systemc solution first.
    1 point
  42. TLM payload is used for untyped raw data transfers. Data format is usually a property of device. Let's consider an example: Initiator is CPU model, and target is Convolution filter accelerator. Accelerator accepts a 2d matrix (2d array) of coefficients as an input. Documentation of accelerator must specify a binary format of data, for example: coefficients are stored in row-major order, each coefficient is 8-byte signed integer. Using this documentation initiator converts 2d array into a raw data of tlm payload. And device model converts raw data back into 2d array. This is how i
    1 point
  43. If you use SC_THREAD that means that you are using sc_event under the hood. Because every SC_THREAD in SystemC has event that activates the process. You can for example spawn a SC_THREAD process to do delayed assignment like this: #include <systemc.h> struct spawned_assignment_demo : sc_module { SC_CTOR(spawned_assignment_demo) { SC_THREAD(test_thread); } sc_signal<int, SC_MANY_WRITERS> out{"out", 0}; void print_out_value() { cout << " out value = " << out.read() << " at " << sc_time_stamp() << "\n"; }
    1 point
  44. Than you have a typo in another place: class target : public sc_module { public: sc_export<sc_signal_in_if<bool> > in; ---- > Change to sc_export<sc_signal_inout_if<bool> > in; sc_signal<bool> sig; target(sc_module_name name){in(sig);} }; The problem is that you try to bind port and export with different interfaces
    1 point
  45. this sounds like a bug. normally the sequence and/or items do know on which sequencer they run on *or should run on". there are a few situations where that in of is/was missing. a recent issue i remember was one where when an item was sent to a low level bfm sequencer from a virtual sequence running on a null sequencer then the sequencer info was wrong leading to similar fails.. /uwe
    1 point
  46. SystemC TLM is a part of the SystemC standard (both parts TLM1 and TLM2). True, it is an newer addition, but it is never-the-less part of the standard. TLM1 was the first attempt to standardize an API, which worked, but it didn't address the needs of the SystemC community as well as had been hoped. TLM2 standardizes a methodology to model address mapped bus communications and the associated API. It allows for easier exchange of IP blocks for simulation. TLM emphasizes that "ports" are not just wiring connection points, but rather a nexus for higher levels of communication. TLM2 has "so
    1 point
  47. Rahul, after fixing the missing '$' at the beginning of your vcd dump, I got the following error on GTKwave: GTKWave Analyzer v3.3.49 (w)1999-2013 BSI Near byte 206, $VAR parse error encountered with 'SystemC.Enable' Near byte 252, $VAR parse error encountered with 'SystemC.output' No symbols in VCD file..nothing to do! As you can see, there is an error in your VCD file (at least according to GTKwave): You use spaces in your signal names. Replace those with '_' or something similar, and your VCD viewer should be happy. hth, Philipp
    1 point
  48. Hi, declaring a class virtual means that the class itself cannot be instanced - it must be extended. So you can't make an instance of uvm_scoreboard on its own. However uvm_scoreboard is itself derived from uvm_component. uvm_component has a constructor (new function) which needs the two arguments (name and parent). If you derive from a base class and don't write your own constructor in the derived class, then the default constructor will get called. If the default constructor is called, then the standard says (1800-2012 p145) "super.new call shall be the first statement execu
    1 point
  49. Hi Amit, I didn't say "Concept of multiple interfaces in sc_export is a benefit of sc_export over sc_port". I said "You have to parameterize the export by the interface. So if you have two interfaces, and you want them to be exported by a single export, you'd have to create a derived class." You can do that with sc_port as well (i.e. use a single derived class interface that is derived from another set of interface classes) - see the code for sc_inout, for instance, regards Alan
    1 point
  50. apfitch

    Memory mapped bus ??

    When TLM2 was developed, the main requirements were speed interoperability To achieve interoperability, it was decided to standardise the generic payload object. The design of the generic payload was aimed at allowing modeling of memory-mapped busses. A memory-mapped bus uses an address in memory to locate the registers/memories in peripherals attached to a bus. So the generic payload includes a field for address, as well as fields for data. regards Alan
    1 point
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