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  1. Actually the usual bus protocols allow to send larger number of requests and the interconnect is allowed to answer them 'out of order' (e.g. AMBA AXI or CHI). But you are free to define you onw protocol and its own rules. The LRM states exactly how to do this. One example can be found at https://github.com/Arteris-IP/tlm2-interfaces which defines the extensions and phases for the AXI/ACE and the CHI protocol.
    2 points
  2. Hello @berry_runner, Regarding a dedicated training look here: https://www.doulos.com/training/ But as a starter in this, I would recommend getting to know following in no particular order: C++11/14/17: Useful for writing concise and clean code. SystemC from Ground Up 2nd Edition by @David Black. https://github.com/dcblack/SCFTGU_BOOK/ Look into the examples directory in SystemC sources. https://github.com/accellera-official/systemc/tree/master/examples Look into publicly released projects on Github: https://github.com/topics/systemc
    2 points
  3. Just to add 2 cents to @David Black proposal: If the instantiation is exepensive you could fork() (https://en.wikipedia.org/wiki/Fork_(system_call)) your programm after instantiating the design. Basically you create a new OS process as copy of the current one and here you can continue the simulation. But in essence it is the same approach as David described.
    2 points
  4. The primary reason is that the SystemC Proof-of-Concept (PoC) implementation uses some global data structures, which get constructed during elaboration, which are not fully cleaned up when sc_stop() is called. These data structures are only freed by the OS when the application quits. There have been some efforts improve the PoC implementation in this area, but these are currently stalled. Unfortunately, partially due to bad code examples, bad habits, and laziness, many SystemC models also not cleanly deallocate their dynamically allocated resources, as they still use manual resource allocation
    2 points
  5. You cannot bind an output port to an input port. Ultimately each port must bind to a signal either hierarchically (this is where port to port binding can is used) or directly. So you need to define signal for each of the test_module output ports and bind the sc_out and sc_inout ports to it. 2 remarks: you should use sc_in instead of sc_inout to indicate the purpose clearly sc_out is just a child of sc_inout to reduce the number of output ports (and hence signal) you might want to group signals logically belonging together into structs. Those can be used as data typs of si
    2 points
  6. Port requires a pointer towards the object containing implementations of methods specified in the interface. Export provides the very pointer that port needs. Port goes from caller towards callee. Export goes from callee towards caller. Pseudo-graphically: // +----------------------------------------------------------------------------------+ // |struct Top : sc_module { | // | | // | initiator.p1.bind( target.x1 );
    2 points
  7. David is correct, another program having issues with Quickthreads is valgrind. With Quickthreads SystemC threads actually all live in a single pthread. When a SystemC thread yields to another one the stack is changed from one piece of storage to another in a discontinuous manner. The stack for that single pthread that SystemC is living ends up being discontinuous. With pthreads enabled each SystemC thread is in its own pthread and those stacks are continuous.
    1 point
  8. uvm_config_db is simply a facade pattern on top of the uvm_resource_db. As mentioned above, most recommend avoiding direct use of the resource db because the config db adds more consistency to its use.
    1 point
  9. The simple answer is that SystemC does not know how to trace std::string, and much less and array of std::string. First, std::string is a dynamically variable array of characters, which will perplex waveform viewing because you need a fixed number of signals to display. Changing to a fixed std::array<char,10> would help. You would still need to write an overload something like: template<int depth> void sc_trace( sc_trace_file* tf, const std::array<char,depth>& A, const std::string& name ) { // Code to trace individual char's for(int i=0; i<depth;
    1 point
  10. Yes, it is possible. Since SystemC is basically a C++ class library you can you whatever C/C++ allows for.
    1 point
  11. You'll have to create internal (i.e., private) signals for each member of the bundled class, which you need to connect to sub-blocks. Then, you have to register a SC_METHOD or SC_THREAD, which is sensitive to changes of the bundled input. The method/thread can then assign the correct new values to the internal signals based on the changed bundled input.
    1 point
  12. Not sure if this topic is active. Here is some feedback. 1. Decouple the datatypes library from other core SystemC libraries. In other words it should be a light stand-alone library of its own. 2. Single unified bit vector library for all widths (like ac_int<W>). However having the range function for behavioral modeling (not synthesis) is also very useful. Currently we use the following c++-11 feature: /*----------------------------------------------------------------*/ // This uses a neat template alias trick introduced in C++-11 // to hide the underlying type of either a
    1 point
  13. On a side note, you might also consider moving to SystemC 2.3.3; SystemC 2.3.1 is fairly old.
    1 point
  14. SystemC is a discrete event driven simulator using an approach similar to Verilog, SystemVerilog and VHDL.The coding approach assumes cooperative multitasking. This is very time efficient and more importantly simplifies the modeling aspect if you really understand it, and makes it easier to interoperate with other simulators. Immediate notification is a unique feature of SystemC that works for some models, but not all. The reasoning behind it is simple efficiency. Delayed notification (i.e., SC_ZERO_TIME) is the safest approach if you are not certain that other processes are designed to w
    1 point
  15. Paul Floyd

    A few Valgrind issues

    Here is a full analysis of the first problem, and a proposed patch. Here's what I saw running the executable under Valgrind via the GDB server (this is required to execute the mo(nitor) command). 257 result_p->digit = (sc_digit*)sc_core::sc_temp_heap.allocate( 258 sizeof(sc_digit)*result_p->ndigits ); 259 #if defined(_MSC_VER) 260 // workaround spurious initialisation issue on MS Visual C++ 261 memset( result_p->digit, 0, sizeof(sc_digit)*result_p->ndigits ); 2
    1 point
  16. Have a goal. Do you want to learn the design side or verification? Either way, create some small design, then a testbench to check its operation. There are a lot of great resources out there. Sometimes you can get a simulator license by taking a course. Or use the EDA Playground. Stu Sutherland has an excellent book on design with SystemVerilog. Highly recommended! Personally, I learned a lot by writing many small examples. You can do a lot in a dozen lines. I have a directory filled with little modules, most under 20 lines. If you keep it small, you can stay focused. Once you h
    1 point
  17. Paul Floyd

    A few Valgrind issues

    More details on the other two issues systemc/misc/user_guide/chpt4.4 ==165605== Invalid write of size 8 ==165605== at 0x49FACA6: sc_core::sc_object::orphan_child_objects() (sc_object.cpp:336) ==165605== by 0x49F5D46: sc_core::sc_module::~sc_module() (sc_module.cpp:273) ==165605== by 0x406CC3: stage1_2::~stage1_2() (stage1_2.h:43) ==165605== by 0x406B95: pipeline::~pipeline() (pipeline.h:43) ==165605== by 0x406C38: pipeline::~pipeline() (pipeline.h:43) ==165605== by 0x49F5343: sc_core::sc_module_dynalloc_list::~sc_module_dynalloc_list() (sc_module.cpp
    1 point
  18. This part is wrong: for ( int i=0; i<N ; i++){ for ( int j=0; j<NB_elements_trans ; j++){ i_adder = new adder("i_adder"); i_adder->in[j](sig_data[i][j]); } i_adder->out(sig_add); } You create N x NB_elements_trans i_adder elements and on each of them you only connect 1 of 4 in ports. I guess you mean: for ( int i=0; i<N ; i++){ i_adder = new adder("i_adder"); for ( int j=0; j<NB_elements_trans ; j++){ i_adder->in[j](sig_data[i][j]); } i_adder->out(sig_add); } A few remarks: you create a memo
    1 point
  19. Hello @Beginner_KOR, You can follow a similar discussion here: Hope this helps. Regards, Ameya Vikram Singh
    1 point
  20. Hello @Issraa, Can you share the directory listing(ls -al) for the mentioned path below: ls -al /home/israa/systemc-2.3.3/ # or more appropriately ls -al $SYSTEMC_HOME Regards, Ameya Vikram Singh
    1 point
  21. In the constructor list you would provide a creator function. This is a functor(a function pointer, a std::function object, a Functor classinstance, a lambda function, ...) which accepts a char const* and a size_type and returns a constructed object. In your case it would look like (C++11): class example: public sc_core::sc_module { public: sc_core::sc_vector<sc_core::sc_fifo<unsigned>> fifos; example(sc_core::sc_module_name nm, unsigned outputs) : sc_core::sc_module(nm) , fifos("fifos", outputs, [](char const* name, unsigned i)->sc_core::sc_fifo<unsigned&g
    1 point
  22. SystemC FIFO's represent hardware and as such may only be created during construction of a model. After elaboration closes, you are not allowed to add more fifos. None of your code examples above are complete, so it is fairly hard to give you a complete answer. Perhaps you could put your design on https://edaplayground.com and share a link with us. For details on phases of SystemC (e.g. elaboration) see IEEE-1666-2011.pdf, which you can obtain through Accellera.org.
    1 point
  23. Hello @Beginner_KOR, I would recommend going through details on SystemC TLM modeling using the following resources in no particular order: SystemC Standard document: IEEE 1666-2011(Must read) SystemC from Ground Up 2nd Edition by @David Black. https://github.com/dcblack/SCFTGU_BOOK/ Looking at SystemC TLM examples in the SystemC Sources: https://github.com/accellera-official/systemc/tree/master/examples/tlm SystemC TLM-2.0 examples on EDA Playground: https://www.edaplayground.com/playgrounds?searchString=&language=C%2B%2B+only&
    1 point
  24. The SystemC standard says: 5.10.8 Multiple event notifications A given event shall have no more than one pending notification. If function notify is called for an event that already has a notification pending, only the notification scheduled to occur at the earliest time shall survive. The notification scheduled to occur at the later time shall be cancelled (or never be scheduled in the first place). An immediate notification is taken to occur earlier than a delta notification, and a delta notification earlier than a timed notification. This is irrespective of the order in whi
    1 point
  25. Actually this is a Virtualizer specific question so you are better up contacting SNPS directly or try their SolvNet. But if you have missing symbols during link you miss to specify a library. How to solve this is a question to SNPS.
    1 point
  26. This is not really a memory leak, but a very bad „model“ for the current implementation. I wonder if you saw any such scenario in a real model? „Canceled“ notifications like in your case will still be kept in the kernel‘s internal data structures until the notification time is reached (1ms in your case). You would pile up 999,999,999 of these canceled notifications until they are „deallocated“, each of them taking entries in the event queue and 16 bytes for the notification itself. Which is a lot of memory. I wrote „deallocated“ in quotes, because sc_event_timed uses a very simple m
    1 point
  27. Let me start by observing that you probably don't want to initialize an input port. After all, inputs observe information from outside the module. So I will assume you mean an output port. If need be, you could change to use an sc_inout<T> port, but you might create a nasty race condition. The cleanest and most general approach is to write to the port during the start_of_simulation phase. How? Just create a override method, void sc_start_of_simulation(void), in your module. SC_MODULE( Example ) { sc_out<bool> oport{"oport"}; sc_signal<int> local_sig{"local_sig
    1 point
  28. Three thoughts might be helpful for you to consider: You could of course use next_trigger() in SC_METHOD: SC_MODULE(HARD_WAY) { sc_in<bool> clock, clock_enabled; SC_CTOR(HARD_WAY) { SC_METHOD(gated_method); sensitive << clock; ... } ... void gated_method(void) { if ( clock_enabled and clock.posedge() ) { // Normal operations } else { // Wait until clock is re-enabled next_trigger( not clock_enabled ); } } The better way is to use sc_process_handle::disable() and enable() #define SC_INCLUDE_DYNAMIC_PROCESSES #incl
    1 point
  29. @omaima RTFM please. It's all in the README and related files. Better yet, signup and take a class from somebody.
    1 point
  30. I guess your problem stem from a particular implementation detail in SystemC: if you have an inheritance hierarchy you should declare all constructor parameters as ' my_module( sc_core::sc_module_name const& nm). For the leaf module can leave it as 'MyModule(sc_core::sc_module_name nm)'. In the second case a copy of the module name is created which manipulates the hierarchy stack of the kernel. I assume this way you srew up your design. It is save to always pass the sc_module_name by const reference in the constructors. This would makeup for a good rule in a modleing guideline
    1 point
  31. Eyck

    tlm to pin converter

    Well, sc_fifo is not TLM. For your example the basic question is: what is the protocol on fifo_out? Should it be clock-based? Valid-Ready signaling? So your queastion and example is too generic and broad. If you are looking for an example to translate from TLM2.0 to pin level of an Amba AHB protocol you may have a look here: https://git.minres.com/SystemC/SystemC-Components/src/branch/master/incl/tlm/ahb/bfm and https://git.minres.com/SystemC/SystemC-Components/src/branch/master/src/tlm_ahb_bfm_initiator.cpp as well as https://git.minres.com/SystemC/SystemC-Components/src/branch/mas
    1 point
  32. Hello Suhyun, Yes you are right on Q1 and Q2. On Q2, you miss one zero. It should be 0x40001 rather than 0x4001. Best regards, Erwin
    1 point
  33. Basically yes but just add_attribute is not enough. From the top of my head: you need to declare in your sc_module: sc_core::sc_attribute<A*> attr{"attr", nullptr}; sc_core::sc_in<bool> pin{"pin"}; in the constructor of your sc_module you need to add the attribute to the sc_object/sc_port: pin.add_attribute(attr); via attr.value = new A(); you can assign a value. This way the attribute can be found e.g. via the SystemC object tree (sc_core::sc_get_top_level_objects() ). Alternatives depend of your goal. One option would be to use CCI, esp. cci_para
    1 point
  34. SCV does not contain an the respective overloads for scv_introspection and _scv_distribution. Therefore there is afaik no way to simply randomize a vector. As a workaround you might use the randomization for plain C-style arrays.
    1 point
  35. Yes, I have actually created a post on the MinGW forum that can be found there: https://sourceforge.net/p/mingw-w64/discussion/723798/thread/7b5436a4d9/. I though got nothing. Your suggestion about overhauling this part of SystemC sounds really good. The only concern for me is that C++20 is pretty new and it might require users to upgrade their compilers to provide C++20 support.
    1 point
  36. Hi all, So, I'll start by stating the problem. The problem is that it is not possible to use Quickthreads on 64 bit Windows. Basically, for sake of consistency with other platforms as well as 32 bit Windows, I need to be able to use Quickthreads as well. So, before I begin I have a question: What is the out of the box choice for SystemC threads on Windows platforms both 32 bit and 64 bit? As far as I understand from the configure script, WinFibers is what will be used for Windows if MinGW is being used: # use WinFiber on MinGW platforms
    1 point
  37. My point was more of a generic nature and more related to modeling guidelines. If your initiator/test_producer has many signals some of them might belong 'logically' together as they are written at the same time. E.g in AHB you have HADDR, HTRANS, HBURST, HWRITE, etc. Instead of declaring them as sc_out<sc_dt::sc_logic> xxx or alike: sc_out<sc_dt::sc_lv<32>> HADDR; sc_out<sc_dt::sc_lv<4>> HTRANS; sc_out<sc_dt::sc_logic> HWRITE; . . . it would make sense to do it this way: struct ahb_req { sc_dt::sc_lv<32> HADDR; sc_dt::sc_lv<4&
    1 point
  38. David Black

    About AT

    TLM (Transaction Level Modeling) is focused on communication (interconnection) of SystemC models. So your question is slightly irrelevant. From what you indicate, I would say that AT modeling style would accomplish what you are interested in. Sockets are an almost essential aspect of TLM as they simplify modeling and can provide information about the transaction. As to what metrics you can get, that is up to you. SystemC is not a prepacked set of subroutines, nor is it a narrowly focused on one type of analysis. SystemC is a methodology using C++ to model any variety of ideas using an ev
    1 point
  39. UVM-SystemC 1.0-beta3 was released for public review. Download available at https://www.accellera.org/downloads/drafts-review. Notable changes since 1.0-beta2: Register API Bugfixes & SystemC 2.3.3 support Ubus example Automatic objection mechanism
    1 point
  40. have a look at uvm_enum_wrapper in uvm12+. you could simply do the following (untested) class myenumwrapper#(type T) extends uvm_enum_wrapper#(T); static function bit is_inside(string x); return map.exists(x); endfunction endclass // and later myenumwrapper#(my_enum)::is_inside("alpha") /uwe
    1 point
  41. module who_changed_first(input a, b, start); always @(posedge start) begin byte changed; WATCHERS: fork @a changed = "a"; @b changed = "b"; join_any disable WATCHERS; //< prevent others from overwriting case (changed) "a": work_1; "b": work_2; endcase end Assumes SystemVerilog. If Verilog you will need to add . See https://edaplayground.com/x/2NXz for example code.
    1 point
  42. Dave5144

    Guide/Help for Beginners

    I got the examples to build under VS2019 by modifying the visual studio install to use VS 2015 build tools. It's a box you can click under the C++ install options. I also had to delete the previously downloaded systemC folders then re-download them. Build the VS2010 systemc solution first.
    1 point
  43. Sure. Just add a method reading all bool sc_in and write to the output. You need to make it sensitive to all inputs Something like: SC_MODULE(conv){ sc_vector<sc_in<bool> > input{"input"}; sc_out<bool> ouput{"ouput"}; SC_CTOR(conv){ SC_HAS_PROCESS(conv); SC_METHOD(method); for(auto& in: input){ sensitive<<in; } } void method(){ unsigned res = input[1]?2:0+input[0]?1:0; output=res; } };
    1 point
  44. You dot need a reference to the covergroup class. You can omit this line of code: cg_fsm_state cg_fsm_state_inst; In the constructor you are calling new directly on the coverage class name: cg_fsm_state = new();
    1 point
  45. Since it seems this is not a interesting topic just in case someone is looking for information I came across these papers http://www.verilab.com/files/litterick_register_final.pdf basically claims that factory registration of registers should be avoided to get better performance results Common issues and pitfalls
    1 point
  46. what are the major differences between sc_port and sc_export?
    1 point
  47. TLM payload is used for untyped raw data transfers. Data format is usually a property of device. Let's consider an example: Initiator is CPU model, and target is Convolution filter accelerator. Accelerator accepts a 2d matrix (2d array) of coefficients as an input. Documentation of accelerator must specify a binary format of data, for example: coefficients are stored in row-major order, each coefficient is 8-byte signed integer. Using this documentation initiator converts 2d array into a raw data of tlm payload. And device model converts raw data back into 2d array. This is how i
    1 point
  48. Than you have a typo in another place: class target : public sc_module { public: sc_export<sc_signal_in_if<bool> > in; ---- > Change to sc_export<sc_signal_inout_if<bool> > in; sc_signal<bool> sig; target(sc_module_name name){in(sig);} }; The problem is that you try to bind port and export with different interfaces
    1 point
  49. Hi, declaring a class virtual means that the class itself cannot be instanced - it must be extended. So you can't make an instance of uvm_scoreboard on its own. However uvm_scoreboard is itself derived from uvm_component. uvm_component has a constructor (new function) which needs the two arguments (name and parent). If you derive from a base class and don't write your own constructor in the derived class, then the default constructor will get called. If the default constructor is called, then the standard says (1800-2012 p145) "super.new call shall be the first statement execu
    1 point
  50. apfitch

    Memory mapped bus ??

    When TLM2 was developed, the main requirements were speed interoperability To achieve interoperability, it was decided to standardise the generic payload object. The design of the generic payload was aimed at allowing modeling of memory-mapped busses. A memory-mapped bus uses an address in memory to locate the registers/memories in peripherals attached to a bus. So the generic payload includes a field for address, as well as fields for data. regards Alan
    1 point
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