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  1. Actually the usual bus protocols allow to send larger number of requests and the interconnect is allowed to answer them 'out of order' (e.g. AMBA AXI or CHI). But you are free to define you onw protocol and its own rules. The LRM states exactly how to do this. One example can be found at https://github.com/Arteris-IP/tlm2-interfaces which defines the extensions and phases for the AXI/ACE and the CHI protocol.
    2 points
  2. On a side note, you might also consider moving to SystemC 2.3.3; SystemC 2.3.1 is fairly old.
    1 point
  3. Code itself looks fine. I ran the above on EDAplayground without problem. I also ran on MacOS 10.15.7 (Catalina) with Apple clang++ 12.0 (LLVM ) Here is a link to where I ran it: https://edaplayground.com/x/V25h SystemC 2.3.3-Accellera --- Sep 21 2020 10:55:34g++ 7.5Using C++ standard 201402Ubuntu 18.04 You might consider upgrading g++ (4.8 is pretty old). I use g++ 9.3 normally.
    1 point
  4. SystemC is a discrete event driven simulator using an approach similar to Verilog, SystemVerilog and VHDL.The coding approach assumes cooperative multitasking. This is very time efficient and more importantly simplifies the modeling aspect if you really understand it, and makes it easier to interoperate with other simulators. Immediate notification is a unique feature of SystemC that works for some models, but not all. The reasoning behind it is simple efficiency. Delayed notification (i.e., SC_ZERO_TIME) is the safest approach if you are not certain that other processes are designed to w
    1 point
  5. @plafrattTLM2 is built to allow any protocols you like. The "base protocol" was deemed sufficient for most needs; however, TLM2 was designed specifically to allow alternatives. Furthermore, the standard provides mechanisms to keep the cost of adapters/bridges between protocols simulation efficient. [Plug - ignore if you like] The Doulos course on TLM 2.0 <https://www.doulos.com/training/systemc-tlm-20/systemc-modeling-using-tlm-20-online/> investigates the base protocol and then builds up to a module describing custom protocols.
    1 point
  6. Paul Floyd

    A few Valgrind issues

    Here is a full analysis of the first problem, and a proposed patch. Here's what I saw running the executable under Valgrind via the GDB server (this is required to execute the mo(nitor) command). 257 result_p->digit = (sc_digit*)sc_core::sc_temp_heap.allocate( 258 sizeof(sc_digit)*result_p->ndigits ); 259 #if defined(_MSC_VER) 260 // workaround spurious initialisation issue on MS Visual C++ 261 memset( result_p->digit, 0, sizeof(sc_digit)*result_p->ndigits ); 2
    1 point
  7. Have a goal. Do you want to learn the design side or verification? Either way, create some small design, then a testbench to check its operation. There are a lot of great resources out there. Sometimes you can get a simulator license by taking a course. Or use the EDA Playground. Stu Sutherland has an excellent book on design with SystemVerilog. Highly recommended! Personally, I learned a lot by writing many small examples. You can do a lot in a dozen lines. I have a directory filled with little modules, most under 20 lines. If you keep it small, you can stay focused. Once you h
    1 point
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