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Showing content with the highest reputation on 08/07/2015 in Posts

  1. Hi, SystemC tries to preserve you from implementing undefined behaviour as much as possible. There is an option to allow multiple writers but, in general, this is not what you want. If two processes write to a signal or fifo in the same delta cycle, the order of write accesses is not deterministic. In your case, there are several options: Writing your own channel, e.g. a bus model. Writing some kind of de-multiplexer. ... In all cases, you have to think about what happens if more than one process tries to access the component conrurrently. And you have to define some kind of order between the input ports or a communication protocol. Greetings Ralph
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  2. Hello Sir, As you have found out yourself, multiple writer feature is not supported by the built-in channel classes. Have you looked into the possibility of creating your own channel ? Alternatively, have you considered the option of a shared memory with multiple readers and writers, coupled with blocking reads/writes -- please check the built-in concurrency control classes as sc_mutex, sc_semaphore. Hope that helps.
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