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Showing content with the highest reputation on 09/08/2014 in all areas

  1. cliffc

    Program blocks

    Death to Programs! It took me years to arrive at this conclusion, but I now believe that programs were a bad idea and should be avoided completely. After some convincing by other committee members, I voted for inclusion of programs into the SV Standard and I now regret that vote (please forgive me! ) The idea behind the program was that if an engineer applied stimulus on the active clock edge, the RTL design would completely respond to the clock, then the testbench would calculate new stimulus values on the same clock edge and send them into the RTL design, and any combinational inputs to the RTL design would then update before moving to the next clock edge. The idea was to avoid co-dependent, 0-time race conditions between the RTL and testbench execution. The point of the matter is, although it is a semi-common practice, you should never send stimulus on the active clock edge. In real hardware, this is known as a setup or hold-time violation and is never done. In 0-delay RTL simulations, if done properly, it works (but can be subject to a variety of race conditions). In gate-level simulations (GLS), this will violate setup and/or hold times, which means you have to modify the testbench to run with different timing values to perform GLS. I currently send stimulus using a time-budgeting scheme with my clocking blocks so that stimulus is sent 10%-20% of the clock cycle after the active clock edge (allowing for hold times and to meet long-combinational-input gate-delays). This allows me to use the same testbench for 0-delay RTL and GLS, and closely mimics the behavior of real hardware. If you don't send stimulus on the active clock edge (which you should never do), you don't need a program block. As has already been discussed in this thread, if you use programs, you have confusion, limitations and rules to follow, including the fact that a program cannot instantiate a module, and a module cannot call tasks/functions from a program. Removing programs greatly simplifies testbench development. Programs were a semi-good idea gone bad. As long as you do not have stimulus driven on the active clock edge (which is a bad idea - have I repeated that enough?), you can replace all program-endprogram keywords with module-endmodule. Chris Spear's very good SV Verification book uses programs. I have already informed my good friend and respected colleague that he should change all occurrences of program-endprogram to module-endmodule. I have never needed to use programs and standard UVM verification techniques do not use programs. Program usage is highly discouraged in my training classes. Regards - Cliff Cummings Verilog & SystemVerilog Guru
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