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Showing content with the highest reputation on 12/02/2013 in all areas

  1. 1 point
    Hello Geniuses, in my ADC design, I have a output signal "eoc" (end of conversion), I declared it in port declaration like below sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; In processing function, when I assign it a value '1' like below eoc = '1'; I get following error message A2D.cpp: In member function ‘virtual void a2d_nbit::processing()’: A2D.cpp:50: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:50: error: initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’ I also tried to initialize "eoc" in Initialize function like eoc.initialize('1'); but then my compiler gives me another error as follows A2D.cpp: In member function ‘virtual void a2d_nbit::initialize()’: A2D.cpp:28: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:28: error: initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’ could you please suggest me how can initialize and assign sc_dt::sc_logic port ? thanks in advance, Milind.
  2. 1 point

    TDF VSink issue

    Think of isinks and vsinks as current meters and voltage meters. Like in reality, you have to connect them, respectively, in series to the branch, in which you want to measure the current, in parallel to the branch, across which you want to measure the voltage. So in your case, you have to connect the vsinks in parallel to the resistors. The reinitialization of your equation system error likely stems from the fact that you chose a resistance value of zero (i.e., you short circuited two nodes) for both resistors. In consequence, the current through the voltage source cannot be determined by the solver of the ELN MoC.
  3. 1 point

    synthesizeable systemc code

    Hi is object oriented systemc code synthesizable? for example I defined a new data type (a class) and used it in my code. I don't know I can synthesize it or no. is there any free synthesis tool for systemc? or should I translate my code to Verilog and then synthesize it by existing synthesis tools?
  4. 1 point

    IO port by reference

    Hi All, Can I pass a reference to IO port? The code below results in a Modelsim error which I suspect is because of the sc_out reference SC_MODULE(PROC3) { sc_in<bool > clk; sc_in<bool > reset; sc_in<bool > dbusin; sc_out<bool > dbusout; void doff(const sc_core::sc_in<bool>pin, sc_core::sc_out<bool>&pout) { pout.write(pin.read()); } void entry_clk() { while(true) { doff(dbusin,dbusout); wait(); } } SC_CTOR(PROC3) { SC_CTHREAD(entry_clk,clk.pos()); } }; # ** Error: (vsim-6511) Insert port failed: simulation running: port '/proc3_tb/DUT/entry_clk/port_0' (sc_port_base) # In process: /proc3_tb/DUT/entry_clk @ 55 ns Thanks, Hans.
  5. 1 point
    Hello all, Accellera Systems Initiative annouced the release of the SystemC AMS 2.0 standard. The AMS 2.0 standard is available as Language Reference Manual and can be downloaded here: http://www.accellera.org/downloads/standards/systemc Note that this standards update does not contain the user's guide. The AMS working group is working hard to release this document in the future. Now that AMS 2.0 is available, we anticipate that EDA companies and/or research institutes are getting inspired to make a proof-of-concept compatible with this standard. This means that today there is no simulation platform available, but we expect in the future it will become available. Also ask your preferred EDA vendor or partner when SystemC AMS 2.0 gets integrated in the tool and flow. Feel free to post your questions or remarks on the new SystemC AMS 2.0 standard in this forum. Regards, Martin Barnasconi AMS working group chair
  6. 1 point
    One of the singleton class coding styles is like this: module top; class singleton; static local singleton me = new; local function new (); endfunction endclass: singleton endmodule: top The invocation of "new" constructor is in the class but not in the static function like "get_inst". Simulators don't handle this code uniquely. Please help confirm whether it is allowed by the LRM.
  7. 1 point

    Deleting dynamic objects

    hi all, Normally, in C++, all dynamically created objects (pointer = new object) are deleted after their use is done to avoid memory leaks. This operation can be carried out in a destructor or special function as well. I have seen many SystemC (done by some experts) codes where such objects are not deleted. Is that not required in SC? Also now I am attempting to create a vector of pointers to objects. Shall I delete these objects later or does SC take care of this (I think SC can not do that)? Thank you.
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