Jump to content

Leaderboard


Popular Content

Showing content with the highest reputation on 09/30/2013 in Posts

  1. 1 point
    foster911

    systemC synthesis guidlines

    LegUp 2.0 (an open source high-level synthesis tool) ............... http://legup.eecg.utoronto.ca/download.php http://legup.eecg.utoronto.ca/demo.php or http://legup.eecg.utoronto.ca/getstarted.php .................... About the above demo: The LegUp 2.0 demo will synthesize your C code into Verilog RTL running entirely in hardware (no soft TigerMIPS co-processor). The demo uses the default LegUp settings: Cyclone II FPGA target device, 15ns period constraint, binding enabled for dividers, and pattern sharing enabled. The default code is the MIPS benchmark from CHStone, which implements a MIPS processor and then executes a short MIPS program to sort an 8 integer array. ................... A good thesis for better learning: Enabling Hardware/Software Co-design in High-level Synthesis https://tspace.library.utoronto.ca/bitstream/1807/33380/4/choi_jongsok_201211_MASc_thesis.pdf The HercuLeS high-level synthesis tool: http://www.nkavvadias.com/hercules/
  2. 1 point
    apfitch

    systemC synthesis guidlines

    The short answer is probably "no we can't simplify it" :-) If you want to learn about high level synthesis, you need to a bit of reading. You could start with the Wikipedia article on High Level Synthesis https://en.wikipedia.org/wiki/High-level_synthesis and then there's some useful background information on Forte DS website http://www.forteds.com/behavioralsynthesis/ It might be worth reading the documenation on Vivado HLS (www.xilinx.com) as well, there is some introductory material, for instance this video: http://www.xilinx.com/training/vivado/vivado-hls-in-depth-technical-overview.htm One thing to remember with HLS is that it is not as mature as RTL, so different tools may well have different approaches, regards Alan Try reading those and see if that helps, kind regards Alan
×
×
  • Create New...