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Showing content with the highest reputation on 09/30/2013 in Posts

  1. LegUp 2.0 (an open source high-level synthesis tool) ............... http://legup.eecg.utoronto.ca/download.php http://legup.eecg.utoronto.ca/demo.php or http://legup.eecg.utoronto.ca/getstarted.php .................... About the above demo: The LegUp 2.0 demo will synthesize your C code into Verilog RTL running entirely in hardware (no soft TigerMIPS co-processor). The demo uses the default LegUp settings: Cyclone II FPGA target device, 15ns period constraint, binding enabled for dividers, and pattern sharing enabled. The default code is the MIPS benchmark from CHStone, which implements a MIP
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  2. The short answer is probably "no we can't simplify it" :-) If you want to learn about high level synthesis, you need to a bit of reading. You could start with the Wikipedia article on High Level Synthesis https://en.wikipedia.org/wiki/High-level_synthesis and then there's some useful background information on Forte DS website http://www.forteds.com/behavioralsynthesis/ It might be worth reading the documenation on Vivado HLS (www.xilinx.com) as well, there is some introductory material, for instance this video: http://www.xilinx.com/training/vivado/vivado-hls-in-depth-technical
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