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Showing content with the highest reputation on 04/18/2013 in all areas

  1. 1 point
    Well, there are no dynamic packed arrays in System Verilog. If the logic of your function is independent of the width of the data, as in your example, then you can use a parameterized class that supply you with the required function. For example: class doubler #(int unsigned WIDTH = 1); static task double(ref [WIDTH-1:0] val); val = val * 2; $display("%b",val); endtask endclass module test; logic [3:0] A; logic [7:0] B; initial begin A = 3; doubler #(4)::double(A); B = 5; doubler #(8)::double(; end endmodule
  2. 1 point
    you need to set some_uvm_reg_hw_reset_seq_instance.model to your register model
  3. 1 point
    lisakb1963

    OVM RGM Porting to UVM

    GG, If you have a Register Model for UVM_REG and an adapter, you are good to go for upfront things like reading and writing registers using the UVM_REG API calls. Now you have to decide on how to do prediction (this keeps the register model and the actual DUT synchronized.) Initially you can go with auto-prediction (by default it is off), but eventually you will want to create a predictor for your bus transactions (which tracks both actual bus transactions coming from the register model and other sources.) Turning on auto-predict will monitor your register transactions, but not all the transaction on the bus (outside of the register model.) This known as implicit prediction. Explicit prediction is done when you extend uvm_reg_predictor: Explicit Register Predictor The uvm_reg_predictor class defines a predictor component, which is used to update the register model’s mirror values based on transactions explicitly observed on a physical bus. More on this in 5.9.3 on in the User's Guide Lisa
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