1 pointUVM_REG is a combination of VMM and OVM/UVM RGM. It is the register open standard. Tool generation is vendor specific (there are a lot of third party tools out there too -- which produce IP-XACT 1.5). For Cadence, iregGen takes in IP-XACT 1.5 xml. This makes use of the vendor Extensions. I think RAL has been expanded to produce the register model in SystemVerilog.