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Showing content with the highest reputation on 04/12/2013 in all areas

  1. 1 point

    OVM RGM Porting to UVM

    UVM_REG is a combination of VMM and OVM/UVM RGM. It is the register open standard. Tool generation is vendor specific (there are a lot of third party tools out there too -- which produce IP-XACT 1.5). For Cadence, iregGen takes in IP-XACT 1.5 xml. This makes use of the vendor Extensions. I think RAL has been expanded to produce the register model in SystemVerilog.
  2. 1 point
    David Long

    OVM RGM Porting to UVM

    Hi, The iregGen tool supports both uvm_rgm and the standard uvm_reg classes. I would recommend using the uvm_reg if possible since RGM is not part of the ASI standard. Regards, Dave
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