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  1. struct thread_safe_event_if : sc_core::sc_interface { virtual void notify(sc_core::sc_time delay = SC_ZERO_TIME) = 0; virtual const sc_core::sc_event& default_event(void) const = 0; protected: virtual void update(void) = 0; }; struct thread_safe_event_channel : sc_core::sc_prim_channel, thread_safe_event_if { thread_safe_channel(const char* name); void notify(sc_core::sc_time delay = SC_ZERO_TIME); const sc_core::sc_event& default_event(void) const; protected: virtual void update(void); private: sc_core::sc_event m_event; sc_core::sc_time m_delay; }; // The following may be safely called from outside the SystemC OS thread void thread_safe_event_channel::notify(sc_core::sc_time delay) { m_delay = delay; async_request_update(); } const sc_core::sc_event& thread_safe_event_channel::default_event(void) { return m_event; } virtual void update(void) { m_event.notify(m_delay); }
    2 points
  2. maehne

    Simple AMS examples

    Hello Jens, regarding the late reply due to lack of notification: This is a weakness of the new forum. You have to configure e-mail notifications manually by clicking on your account name on the top right of the web page and then clicking on My Settings. There you can configure to receive e-mail notifications for followed forums and threads. Afterwards, you still have to select the forums and threads to follow. Regarding your actual modeling problem. If you want to model a memristor in SystemC-AMS, then I agree that a TDF-only solution would be preferable. However, then you'll have to make a choice upon model creation on which causality you assume for the Memristor, i.e. how it is operated. Is it driven by a current or a voltage? This will fix its state and output variable. Then, you'll be able to express you memristor equations in a compact TDF model using e.g. an embedded LTF function for the integration of the current and implementing the non-linear M(q(t)) function inside the processing() member function. An implementation combining ELN and TDF will be suboptimal, as it will imply a tight feedback loop between a controlled resistor and a TDF module implementing the non-linear part of the Memristor equations, which has to be broken with a 1 timestep delay. This causes of course a change in the dynamic of your system and in consequence your simulation results will heavily depend on the chosen TDF timestep. Sumit's remarks on SystemC-AMS not being the most suited modeling language for describing circuit-level behavior are valid. LSF and ELN are limited to describing linear (switched) dynamic behavior and trying to model nonlinear behavior with them by combining them with tightly coupled TDF modules leads to suboptimal results. It's a simulation framework intented for the system-level, where most of the circuit level details have been abstracted away to focus on the system architecture and evaluate specifications for whole signal processing and control chains, which contain a significant amount of digital Hw/Sw. In contrast to VHDL-AMS and Verilog-AMS, SystemC-AMS does not offer a nonlinear network MoC, which allows you to solve nonlinear DAEs. Though, Fraunhofer IIS/EAS in Dresden have developed one, which integrates seamlessly into SystemC-AMS, you can check out the publication of Thomas Uhle in SOCC 2010 on it. However, it is not available as open-source. Therefore, VHDL-AMS or Verilog-AMS may still be a more appropriate choice for your needs. Best regards, Torsten
    2 points
  3. sumit_tuwien

    Simple AMS examples

    Dear Jens, when you are so particular about verification/comparison of SPICE design with some reference models, in case of memristors which are quite a strong non-linear device, SystemC-AMS will fail to be beneficial. Without entering the context of linear/non-linear solver, I would like to focus on the reason of this inadequacy is that you want to verify your micro architecture model and SystemC-AMS is a macro-architecture design language (at least most of it). I would like to suggest you to use Verilog-AMS instead. Many people fail to visualize Verilog-AMS as an analog verification language and yours is one such case where back-to-back verification of your spice model can be efficiently performed using Verilog-AMS stimulus and reference model. Please let us know if you still needs help here. Regards, Sumit
    2 points
  4. dakupoto

    Simple AMS examples

    Hello, Could you be a little bit more specific ? For example, you state: "To start with I would like to use simple resistor circuits with a sine voltage for example. This I would than adapt step by step to my final setup." To achieve this, you could simply use SystemC-AMS's ELN framework, along with the TDF framework. The built-in sca_eln:: sca_r class would provide the resistors and the sine wave would come from a TDF module. Converter ports would transfer data back and forth between ELN and TDF objects. Please be aware that the built-in ELN types are all linear, and I doubt you would you would be able to get the memriator hysterisis ("bow-tie") curve with ELN components. Why not use TDF modules only, both to model the sine source as well as the resistor chain, that is use only equations to model the memristor. A few online SPICE examples use similar approach. So, is there something special about the resistor configuration that you are trying to use ? Hope that helps.
    2 points
  5. maehne

    Simple AMS examples

    Hello Jens, I cannot provide you with links to working memristor model for SystemC-AMS. However, a quick search on Google returns relevant material, which may serve as a starting point: http://www.cnr.berkeley.edu/~goster/pdfs/Memristor.pdf http://www.cpmt.org/scv/meetings/chua.pdf http://krex.k-state.edu/dspace/bitstream/handle/2097/4605/KetakiKerur2010.pdf Personally, I like the bond graph formulation (cf. to Karnopp, Margolis, Rosenberg: "System Dynamics") of the memristor model, as it allows for a straightforward transformation of your model into an equivalent block diagram model, which can be expressed using TDF, by means of causality analysis. For the implementation, my hints from my previous post apply. Regards, Torsten
    1 point
  6. One other point - your final wait() is outside the while loop - look at Philipp's code closely, the wait() must be inside the while loop or it will not be used, regards Alan
    1 point
  7. David Black

    Error !

    Turning off warnings for core features that have been deprecated is probably asking for trouble.
    1 point
  8. maehne

    Simple AMS examples

    Hello Sumit, If I understand this forum correctly, then Newbie is a reputation automatically determined by: the number of posts the number of likes you receive by others on your posts, and maybe the number of friends you have on the forum. So it may make sense to take the time to "like" the posts you find valuable. Best regards, Torsten
    1 point
  9. There is no real tutorial example available, yet. But you can look at the SystemC regression tests [1], which have a small test included at tests/systemc/1666-2011-compliance/async_request_update/ Greetings from Oldenburg, Philipp [1] http://www.accellera..._2-3_2012-07-02
    1 point
  10. You seem to assign a value bigger than 31 to a 4-bit sc_uint, and you have built your SystemC library with DEBUG_SYSTEMC defined. With this symbol defined, the library adds some additional bound (and value) checks. To add a breakpoint in your debugger, you may need to add the namespace to the symbol as well: b sc_core::sc_interrupt_here Alternatively, you can break on the reported file:line position directly (since you know precisely, which error you want to look at). Greetings from Oldenburg, Philipp
    1 point
  11. Hi Sumit, header guards won't necessarily help. They stop two header files being included sequentially - but if you have a function *body* in the header, and include that header in two independent files, you'll still get multiple definitions at link time. My guess is that Timmy is #including a gnoise.cpp. In that case the fix is to make a gnoise.h with the function prototype, with your header guards of course, and include the .h not the .cpp, regards Alan
    1 point
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