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  3. Please look here at Using UVM_LOG in https://verificationacademy.com/cookbook/messaging/usingmessaging
  4. Of course you could not start the program, because a library is not an application. You have to write the simulation application yourself using the library to accomplish your goal. SystemC is not an application. It is a library. You need to be suitably proficient in C++ programming to accomplish the tasks.
  5. I am new to UVM and SystemVerilog. For an effective debugging, I wanted to log my transactions coming from the DUT to the monitor into a text file. Since monitor converts into the transaction format, it becomes easy to log the transactions from monitor but I could not find a workaround to do this task. Can someone help with a solution to this problem? Currently, i am using the AHB protocol and I need to keep track of those AHB transactions coming from the DUT. I need to record the address, Read/Write, count, Data to be read/written and time stamps.
  6. I'm trying to install SystemC 2.3.3 on my Windows system(64 bit), but facing error . Please someone help with installation and also suggest if I missed something . Followed below mentioned steps: 1. Installed Microsoft visual studio 2019 2.Downloaded systemc package from Accellera. ( SystemC 2.3.3 (Includes TLM) Core SystemC Language and Examples (tar.gz) https://www.accellera.org/downloads/standards/systemc 3.Opened SystemC.sln from visual stdio. Path- C:\Users\*\Downloads\systemc-2.3.3 (1).tar\systemc-2.3.3 (1)\systemc-2.3.3\msvc10\SystemC 4.When tried to build solution, facing attached error.
  7. I am trying to incorporate FC4SC into our SystemC structure, we have multiple modules and we want to capture SFS with FC4SC, we have a BaseCoverModel and I wanted to know if i want to disabled some Coverpoints in a sub class, can someone tell me how we can do that ?
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  9. Hi, I'm trying to understand if there's the chance of bind a vector of 4 sc_signal<bool> with an sc_signal<sc_uint<4> > I have a Ripple Carry Adder composed of 4 1-bit Full Adder. I create and bind my RIpple Carry Adder with the below code sc_vector<sc_signal<bool> > Gen_1; Gen_1.init(N); sc_vector<sc_signal<bool> > Gen_2; Gen_2.init(N); sc_signal<bool > Cin; sc_vector<sc_signal<bool> > Out; Out.init(N); sc_signal<bool> Cout; Where Gen_1 and Gen_2 are the input signals, Cin and Cout are the carry IN and OUT and Out is the output signal I bind the ports with the following method sc_vector<sc_out<bool> >::iterator itout; sc_vector<sc_in<bool> >::iterator itin; RIPPLECARRYADDER fulladd_0("RIPPLECARRYADDER",N); itin = fulladd_0.FirstNum(Gen_1); itin = fulladd_0.SecondNum(Gen_2); itout = fulladd_0.AddOut.bind(Out); fulladd_0.Cin(Cin); fulladd_0.Cout(Cout); Where FIrstNum, SecondNum and AddOut are sc_vector<sc_in<bool> > FirstNum; sc_vector<sc_in<bool> > SecondNum; sc_vector<sc_out<bool> > AddOut; In the RippleCArryAdder.h Now, I have a module which has an input port in the form of sc_signal<sc_uint<4> > ALUout; Is there a way to bind Out with ALUout for example?
  10. You dot need a reference to the covergroup class. You can omit this line of code: cg_fsm_state cg_fsm_state_inst; In the constructor you are calling new directly on the coverage class name: cg_fsm_state = new();
  11. I agree with @AmeyaVS that it would help if you could share the current state of your modifications in form of a .diff file in this forum or as a work-in-progress pull request on the public SystemC repository on GitHub. Then more people can have a look to maybe suggest a fix for the second half of the issue. It would be great if this long-standing issue regarding QuickThreads on Cygwin64 could be finally fixed.
  12. How proficient are you with C++? Have you read IEEE-1666-2011 (download for free via accellera.org)? Have you downloaded an read all the documentation that comes with the Proof-of-Concept library for SystemC (version 2.3.3)? There are examples and documentation there. Have you visited edaplayground.com? There are limited examples there. Do you hold a degree in Electrical Engineering or Computer Science? Have your read the book, SystemC: From the Ground Up? It contains exercises. You can find associated files at https://github.com/dcblack/SCFTGU_BOOK/blob/master/README.md You will also find some examples on GitHub at various locations. Here is one (I have several others including some currently under development): https://github.com/dcblack/ModernSystemC
  13. hello everyone, I need your support, i was searching for practical examples on systemc, but i unable to find out, how to get examples of systemC for practice purpose. and please tell me how to get training online, for systemC. Thanks and regards Arjun
  14. Hi, I am trying to take instance of covergroup but unable to take it. Getting compilation instance. class model extends uvm_component; `uvm_component_utils(model) bit [2:0] state; covergroup cg_fsm_state; c1 : coverpoint state; endgroup cg_fsm_state cg_fsm_state_inst; function new(); cg_fsm_state_inst = new(); endfunctiion endclass Using above code, getting compilation error as mentioned below Error-[SE] Syntax error Following verilog source has syntax error : token 'cg_fsm_state' should be a valid type. Please declare it virtual if it is an Interface. "/vobs/cores/infrastructure/cia_resourcecontrol/aon_mod_verif/sim/models/./aon_mod_fsm_ref_model.sv", 208: token is ';' cg_fsm_state cg_fsm_state_inst; Regards, Smit
  15. Hi all, I'm trying to create a DLL for a simple SystemC model using Microsoft Visual C++ 2019. After building SystemC DLL (DebugDLL) and following MS doc to create a DLL, I'm having linking errors like: 1> Creating library <path>\SimpleLib\Debug\SimpleLib.lib and object <path>\simple\SimpleLib\Debug\SimpleLib.exp 1>SimpleLib.obj : error LNK2019: unresolved external symbol "__declspec(dllimport) public: __thiscall sc_core::sc_module_name::~sc_module_name(void)" (__imp_??1sc_module_name@sc_core@@QAE@XZ) referenced in function "public: __thiscall myclass::myclass(class sc_core::sc_module_name)" (??0myclass@@QAE@Vsc_module_name@sc_core@@@Z) 1>SimpleLib.obj : error LNK2019: unresolved external symbol "__declspec(dllimport) public: __thiscall sc_core::sc_simcontext::sc_simcontext(void)" (__imp_??0sc_simcontext@sc_core@@QAE@XZ) referenced in function "class sc_core::sc_simcontext * __cdecl sc_core::sc_get_curr_simcontext(void)" (?sc_get_curr_simcontext@sc_core@@YAPAVsc_simcontext@1@XZ) (attached complete log) What could be the problem? The code is the one from the post link: // SimpleLib.h #pragma once #ifdef SIMPLELIB_EXPORTS #define SIMPLELIB_API __declspec(dllexport) #else #define SIMPLELIB_API __declspec(dllimport) #endif #include <systemc.h> class SIMPLELIB_API myclass : public sc_core::sc_module { public: myclass(sc_core::sc_module_name name); void display(); }; //SimpleLib.cpp #include "pch.h" // use stdafx.h in Visual Studio 2017 and earlier #include "SimpleLib.h" myclass::myclass(sc_core::sc_module_name name) : sc_core::sc_module(name) { std::cout << "Inside cons\n"; } void myclass::display() { std::cout << "Calling display\n"; } Configuration of the SimpleLib project was done also following INSTALL (Building against a SystemC DLL): C/C++ -> General -> Additional Include Directories is set to: <my_path>\systemc-2.3.3\src Added SC_WIN_DLL to: C/C++ -> Preprocessor -> Preprocessor Definitions Linker -> General -> Additional Library Directories is set to: <my_path>\systemc-2.3.3\msvc10\SystemC\DebugDLL log.txt
  16. First: I'm not going to solve your problems. I only propose possible solutions. So don't expect read-to-use models Second: doing wait() in an SC_THREAD or SC_CTHREAD creates an implicit FSM. I guess this is not what you want. And as you already noticed, it does not solve you problem. You have a syncronous design and you should model it like that. Third: if your latency is not what you want you need to change your model. Maybe there is a stage to much, maybe there aren't enough. This is left to the modeler....
  17. Hello @mo_ayman, Well you could get it early for review comments from the people in SystemC LWG. Plus people with similar setup to yours can also take a jab at it in getting it fixed. Regards, Ameya Vikram Singh
  18. Hello @AmeyaVS, Yes, for sure this is possible. I would be glad to do such thing. Point is what I have done hasn't 100% fixed the issue. So, that doesn't count as a fix. If I reached a fix, I will gladly share it on the SystemC github. I was hoping someone would be able to help me with that part which is basically the second part of the issue. Thanks
  19. You have several errors due to: Failure to specify the compile-time option '-std=c++11' when using C++11 syntax. Compiler defaults to C++03. 'using namespace std' in conjunction with a global named 'array'. std::array<T> is a new templated class in C++11 and conflicts. Changing references from 'array' to '::array' solves the problem. It would be better to rename it to something that does not collide (e.g. data_array) or remove the 'using' clause and properly provide the correct 'std::' prefix where appropriate. Failure to use uniform initialization of a variable used as a global. As of C++11. When creating a global use the syntax 'TYPE VARNAME { CONSTRUCTOR_ARGUMENTS };' This also works for class members. Specifying global variables that should really be private class members (e.g. count). Solved by moving the declarations to the header file and using uniform initialization. Note that use of globals is generally (including this case) a very poor design decision. Note also the use of '#include "systemc.h"' is frowned upon in many circles. Use '#include <systemc>' (without the '.h') instead. You need to take a proper course in modern C++ to avoid C++ syntax errors. These are novice C++ errors. This forum is for real SystemC issues, not C++ syntax.
  20. The problem with your suggested solution is that it is not giving the correct latency value of the pipeline which is my only target. Note that I already know the latency (in terms of number of clock cycle) of the pipeline which is same as the number of stages. I also understood that FIFO is better way to do handshaking but the FIFO is not delaying in any pipeline stage. So there is no correct latency value. I think that only wait() can pause the simulation but it is only possible in SC_THREAD or SC_CTHREAD and not possible in SC_METHOD. Currently, if I change the SC_METHOD to SC_CTHREAD, it is not giving correct result. I don't know why because just changing SC_METHOD to SC_CTHREAD without changing the code should not make the simulation to fail.
  21. link to code and problem expalanation https://www.edaplayground.com/x/3RvD convLayer convLayer.tpp FIFO.h FIFO.cpp convL2.h convL2.cpp main.cpp
  22. Hello @mo_ayman, Would it be possible to share the changes you have done on the official systemc github repository as a pull request? That would be a better alternative to get the fixes in somewhat faster. Regards, Ameya Vikram Singh
  23. So, what's the expected way to be used to enable SC_THREAD on Windows 64 bit? I have ran into this issue which was crashing in the call *%rax. After some investigation, I knew that as opposed to Linux on Windows different registers are used for the parameters passed to functions. On Linux 1st to 4th parameters are: rdi, rsi, rdx, rcx On Windows 1st to 4th parameters are: rcx, rdx, r8, r9 So, I modified iX86_64.s according to the info above and the call *%rax was executed successfully. I however faced another issue which was that the leave instruction did nothing (the stack wasn't actually unwound and 0x0 was what is left on the stack): So, after the ret instruction it crashed as it tried to execute 0x0 which is not possible.
  24. Dynamic threads have sc_process_handle's that can be used to distinguish them from one another. Dynamic processes can also have arguments passed when they launch by value, reference and const reference. So processes are not a problem. Vectors of sc_event's should be fine (because they are not considered as elaboration time only objects), data structure can be done the same. Ports and modules on the other hand are somewhat problematic; however, you could allocate sc_vector's of these with a fixed upper limit; however, connectivity must be fixed at elaboration. You will of course need to manage the configuration information as to how you use these. I suspect that once you properly define the parameters of your design, it will all be possible. I suggest you first draw a diagram illustrating what you are attempting to do and describe the application. You certainly cannot have an open-ended "I want it to do everything". So please indicate the bounds and time relevant information. Perhaps provide a UML sequence diagram to give a better idea of the dynamic nature required.
  25. I want to share some modules; something similar to when HW threads share the same physical core, but they run different SW threads. My idea is that I need vectors of events and data structures. When using static threads, I cannot change simply and safely the thread, and actually, I need to repeat the code for the threads., Even if I use dynamic threads, and can have parameters, the processes must be distinguished and I need several handles. I would need something as when an item on an event vector sends notification, the shared common code receives the index of the item in the vector. Quite similar as the different instantiations of an object share the code, but not their data. Is there any mechanism for what I want to do?
  26. Just as explanation: pos() returns an event_finder (a proxy object which allows to use an event which is not yet available) while posedge_event() returns the event itself. And the operator|() is ony defined for sc_event.
  27. I fixed the error: For anyone else wondering. Please use: wait(incoming1.posedge_event() | incoming2.posedge_event() | incoming3.posedge_event());
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