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  1. Today
  2. Hello Is it possible in ipxact to describe ports which are enclosed in ifdef macro. For example module m( input [31:0] addr, output [31:0] data, `ifdef ABC in abc_in, out abc_out, `endif ); endmodule If yes, how to describe such ports in ipxact. If not, then what is the recommended way to model such RTL IP Thank you
  3. Yesterday
  4. A related question for a model that enables multiple voltage rails. I have an internal signal that is a sc_buffer to enable the rails. For example // signal to write from state machine sc_buffer<bool> raila_en // input to the module raila.rail_en_in(raila_en_wire); if (mystate == RAMPDOWN) { raila_en.write(0); railb_en.write(0); railc_en.write(0); ... When using this in a CTHREAD, I see in the debugger that the first rail gets disabled, skews to zero, but the other two never get disabled. Of course I can connect all the rails to the same input and configure them to stagger the rails correctly but I want to be able to control each enable independently. Should I be using sc_signal<bool> rather than sc_buffer<bool>?
  5. For slightly less typing and better consistency, I suggest using SC_NAMED macro, which was officially introduced in IEEE-1666-2023. It works under SystemC 2.3.3 and newer. Also, for better performance, unless you are synthesizing, I suggest using int32_t instead of sc_int<32>, and bool instead of sc_uint<1>. Anyhow, here is another take on naming ports, modules, and signals: SC_MODULE(rv_thunder) { sc_out<sc_int<32>> SC_NAMED(add); sc_out<sc_int<32>> SC_NAMED(d_dmem_data); sc_out<sc_uint<1>> SC_NAMED(d_memwrite); sc_out<sc_uint<1>> SC_NAMED(d_memread); sc_out<sc_uint<2>> SC_NAMED(doutdmem_mask); //... // Can do the same with modules and signals: Some_module SC_NAMED(other); sc_signal<bool> SC_NAMED(status); The macro SC_NAMED simply translates SC_NAMED(abc) into abc{"abc"}.
  6. The fact that the desired value of RO field doesn't change when you call set() basically means that the RO field shouldn't need any bus access when update() is called.
  7. I understand your meaning. For RW volatile field. It is required to write the register every time the update() is called because the dut value may be different to the desired value since the last access. But for RO volatile field, I don't think it is required to call update() because writing to them is useless. The dut value won't update to the desired value. In my opinion, it is only used to bypass read checking. So I think needs_update() need to change to not writing to readonly register at all.
  8. Last week
  9. Hello @fayz, For your query: I would start by naming all the systemc objects: For e.g.: SC_MODULE(rv_thunder) { sc_out<sc_int<32>> add{"add"}; sc_out<sc_int<32>> d_dmem_data{"d_dmem_data"}; sc_out<sc_uint<1>> d_memwrite{"d_memwrite"}, d_memread{"d_memread"}; sc_out<sc_uint<2>> doutdmem_mask{"doutdmem_mask"}; ..... Hope this helps. Regards, Ameya Vikram Singh
  10. Hello @MarcelCostel, What you are trying to achieve here has meta-stable states in the final NAND logic gates. Can you try you simulation with varying initial states in the generator module for signal D and the clk? On another note I would not recommend using SystemC for modelling at gate level simulation. Regards, Ameya Vikram Singh
  11. I have commented some ports in both SOC and rv-thunder module due to which i think error occurs, plus i had verified the rv-thunder module through testbench,which is working fine, here is updated version of code: https://www.edaplayground.com/x/QQcs Moreover, do you know any way to name these ports, so that it would be easy for debugging i.e Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_4' (sc_out)
  12. You still have the same issue. If you would name your port this would help in debugging since the error message points to the respective port by name. A guess is that you bind the port readsig in the module control to a signal and d_memreadsig of module thunder in the SOC. It is a guess as all the other files are missing on edaplayground You need to keep in mind: a sc_port and hence a sc_in/sc_ouz/sc_inout only forward the functions of a signal. Therefore it can only be bound to a single signal, usually at top level. Another thought: it might be beneficial to write testbenches and unit tests for your leaf modules and then combine them up then you stumble upon sucher errors early on and based on your last increment. This makes it easier and helps you to understand the constraints imposed by C++ and SystemC.
  13. Thanks for replying. We tried y()!=y(prev), it didn't help a lot, the result won't be same with previous one but was still distributed in limited numbers. Besides, it seems dist with "simple_range" works well, but it could not replace dist in every situation, eg “constraint(d()<c())” .
  14. Hi Eyck, We tried CUDD/Z3 sovlers, but didn't try other optional solvers.
  15. It would appear that you are trying to use register numbers or word addresses to specify byte addresses. The registers seem to be 32-bits or 4 bytes wide. Left shift the register number or word address by at least 2 bits to get a byte address that avoids the overlap. Example: } READ_TACH0 @ (0x0a << 2); } READ_TACH1 @ (0x0b << 2);
  16. hey @AmeyaVS, If commented line 83,84 and 23,24 i.e input ports of rv-thunder module and their respective port binding in SOC module line 23 and 24 , now i get error related to output port: Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_4' (sc_out) In file: D:\Download Data\new download\systemc-2.3.4\systemc-2.3.4\src\sysc\communication\sc_port.cpp:235
  17. Hello @fayz, It seems you are trying to bind the following interface on: rv_thunder.d_dmem_out twice once within the rv_thunder module, and once on the SoC module level. This would not work. You possibly start by commenting the line no.: 84 in the design.cpp on the URL you have shared. Plus I would recommend going through the examples directory available with SystemC source/installation package to get a better idea, on using the library for modelling. Regards, Ameya Vikram Singh
  18. The problem occurs when connecting the ports in SOC module(TOP module), am i making a mistake?: Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_6' (sc_in) In file: D:\Download Data\new download\systemc-2.3.4\systemc-2.3.4\src\sysc\communication\sc_port.cpp:235 here is the link of the code: https://www.edaplayground.com/x/JfnT I want to achieve something like this shown in below picture.
  19. Hi, i can't wrap my head around this problem. The program keeps looping and won't advance to the next step. I'm making a D-Latch using NAND Gates and NOT Gates, a Generator to serve as clock and input source and a Supervisor to display the data. I'm attaching a link to my code with everything there and the schema below: https://www.edaplayground.com/x/R6k7 Thank you in advance!
  20. Hi Tonyli, this is a known issue with crave. The results seems to be correct for each run, but the randomization should be more uniform. There have been some updates to crave over the last year so please use the latest version available from https://github.com/accellera-official/crave/. What you can do to improve the quality of the distribution is the prev() statement to filter out previous results in a constraint. Also feel free to report this issue and a testcase to the crave github page https://github.com/accellera-official/crave/.
  21. Hi Friends, I have known about uvm-sc and crave for a while. Recently we're looking for integrating CRAVE into our testbench and did some experiment. However, we met some issues and I'm not sure it's the real issue or we were not using it correctly. 1. not ture randomization code: randv<sc_uint<16>> b,c,d; ALU4(rand_obj* parent =0) : rand_obj(praent), op(this), b(this), c(this), d(this) { constraint(b()<10 && b()>0); constraint(dist(c(),distribution<short>::simple_range(0,20))); constraint(d()<c()); } Result for mutiple times: B: 8 2 4 4 2 2 4 8 4 2 4 4 2 8 2 4 2 2 4 8 4 2 4 4 2 8 2 4 2 2 4 4 2 8 2 4 2 2 8 4 4 8 2 2 4 2 4 4 8 C: 5 5 2 7 18 11 12 4 19 17 17 19 16 16 8 14 15 16 16 16 14 15 2 6 6 1 2 10 10 1 1 1 8 7 16 16 4 13 17 D: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 It seems b is not B & D were not turely randomized. We have checked the seed is different and we tried different solver, the issue still exist. Besides, we tried vector/array randomization, also seeing some issues similar with above, the result is not truly randomized. This is the most blocking issue. We also have some other concerns to consult but the answer to this issue is more important as we may not be able to use it. Thanks everyone and looking forward to some answers.
  22. I want to use SystemRDL to define some registers for a peripheral I2C device. I tried the following spec: regfile eTACHS { name = "TACH registers"; reg { name = "Read tach"; field { desc = "Checksum-byte 0xFF means not ready"; } CHECK[7:0] = 0; field { desc = "All 16bits should be 0x0000"; } ZEROS[15:8] = 0; field { desc = "Value with the RPM"; } TACH[24:16] = 0; field { desc = "Rest of the buffer is discarded"; } RESERVED[31:25] = 0; } READ_TACH0 @ 0x0a; reg { name = "Read tach"; field { desc = "Checksum-byte 0xFF means not ready"; } CHECK[7:0] = 0; field { desc = "All 16bits should be 0x0000"; } ZEROS[15:8] = 0; field { desc = "Value with the RPM"; } TACH[24:16] = 0; field { desc = "Rest of the buffer is discarded"; } RESERVED[31:25] = 0; } READ_TACH1 @ 0x0b; }; addrmap fan { name = "FAN registers"; eTACHS TACHS; }; The data size for each I2C command is 32 bits. The above rdl when I tried to `dump` it, I got the following result: peakrdl dump fan_i2c.rdl fan_i2c.rdl:36:7: error: Instance 'READ_TACH1' at offset +0xB:0xE overlaps with 'READ_TACH0' at offset +0xA:0xD } READ_TACH1 @ 0x0b; ^^^^^^^^^^ fatal: Elaborate aborted due to previous errors My I2C peripheral device is a set of commands like: READ_TACH0 = 0x0a READ_TACH1 = 0x0b .... The are many commands like that. With SystemRDL, would it be possible to define a RDL for I2C slave register map ? Maybe some way to avoid overlaps errors ? Well, I could find a RDL example for I2C specification. Thanks
  23. Earlier
  24. I think inside do_predict(), the idx should be from the mirrored value. int unsigned idx = m_idx_fld.get_mirrored_value();
  25. Hello @AmeyaVS I resolved it by increasing the amount of memory mapping allowed by the Linux kernel by setting the parameter vm/max_map_count. The command is sudo sysctl vm/max_map_count=<number> Thanks for your suggestions. Regards, Perrin NT.
  26. Hello @Perrinko9105, I would suggest to use a debugger to narrow down the source location from where the std::bad_alloc is thrown. Also, if possible can you share additional context on the source, just have a snippet does not provide enough context. I would prefer if you can share a minimal example which is causing this failure. Regards, Ameya Vikram Singh
  27. Hello @AmeyaVS, All instances are already create within top-level constructor. The top-level module is instantiate using std::make_unique<top>("") statement. They should be stored within the heap. The simulation crashes at the early stage of the simulation. I am suspecting during objects instantiation. Regards
  28. Hello @Perrinko9105, Can you move your top-level SystemC object to heap? It might help to mitigate the issue. Regards, Ameya Vikram Singh
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