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  1. Yesterday
  2. Dear fellows, I just downloaded systemc2.3.3 and when i generate the test exe (using make check) i get an error at link : undefined symbol in libsystemc.a(sc_simcontext.o):sc_simcontext.cpp:(.text+0x6704): undefined reference to `sc_core::sc_cor_pkg_qt::sc_cor_pkg_qt i had no problem to build the libs (libsystemc.a , libsysc.a, libtlm_core.a and libtlm_utils.a) but apparetnly the libsystemc.a contains unresolved reference ? i use MSYS2 with mingw64 and before building, i set the CXXFLAGS variable : CXXFLAGS='-O3 -g -Wall -Wextra -Winvalid-pch -Wno-unused-parameter --std=gnu++11' Please help me , i'm stuck 😞 Thanks in advance Best regards JB
  3. Thanks @plafratt for providing these additional details. I have reported this issue to the LWG for investigation. The warning can be probably fixed by default-initialising the tmp in line 235 of sc_fifo.h
  4. Your message is not providing enough information about your environment. Which version of SystemC did you compile. I suggest you to start with the latest released version of the SystemC proof-of-concept library. Did you follow all the instructions found in section "Installation Notes for Windows" of INSTALL.md? Did you compile SystemC as a static library or DLL? Where you able to build and execute the examples coming along with the SystemC library? Did you also follow the instructions for "Creating SystemC Applications" when you compiled your test program? If you want to link your application against a DLL build of SystemC, you also have to following the instructions in the section "Building against a SystemC DLL". Especially, when running the simulation, your SystemC DLL needs to be in the PATH!
  5. Have you tried to compile and run a simple hello-world-style C++ program in the same environment, from which you called configure? The config.log shows that your PATH contains the bin directories of many different EDA toolchains. Some of them come before the bin directories of your host OS. This may cause issues as these EDA toolchain installation tend to include a lot of basic libraries, which are normally provided by the host OS. This can cause interferences. You may try configure and build SystemC in an environment, where the PATH got pruned of all the EDA toolchain bin paths.
  6. Last week
  7. Why would you want to change the address after sending it? Actually only interconnect components are allowed to change the address of an transaction (this is what the standard says). I would alwys keep in mind how this is handled in haerdware.... One option to address this is to add an extension to your transaction holding the original adress and other information you need. But this comes at the cost of interoperability (if this is a criteria for you). BR
  8. I have recently modeled registers as simple unions to represent bitfields, for example: typedef union { struct { uint32_t ADDRESS:5; uint32_t RESERVED:26; uint32_t ENABLE:1; } b; uint32_t w; } register_type; which facilitates the access to either the complete word or a bitfield. The interesting part comes when I try to check if the register value has changed, is there a more elegant way of doing this than polling in if or while statements for each register's value? I need to do this for a lot of them so I was wondering if modeling this using sc_bv provides a built-in event I could use in a SC_METHOD sensitivity list? example: typedef union { struct { sc_bv<5> ADDRESS; sc_bv<26> RESERVED; sc_bv<1> ENABLE; } b; uint32_t w; } register_type; and then do something like: register_type Reg; ... SC_METHOD(some_method); sensitive << Reg.b.ENABLE; ... some_method(){ ... } Any pointers or ideas are greatly appreciated
  9. Hello Everyone, I'm trying to install SystemC onto Visual Studio 2017. I followed the instructions found in the INSTALL text file, but I am having a Linker error. Hopefully some here can point me to the right direction. Thank you, J
  10. Thank you for the thoughts. I am using acquire() and release() to ensure that the memory is safe while I am using the transaction in the target. The specific problem I am facing is that the initiator might call, for example, set_address() on the transaction after it receives the response, while the target is still using it. The target needs access to the original address.
  11. Since you are talking about timing I would stick to a more AT like modeling style using the non-blocking transport functions. In this case you should use a memory manager (see section 14.5 of the IEEE standard). For this you need to implement the tlm::tlm_mm_interface (there a few implementations out there, you may google them). The mechanism works similar to a C++ shared pointer. The initiator always pulls a new transaction from the memeory manager and sends via its socket. Each component dealing with the transaction calls acquire() on the payload and release() once it is finished with it. Upon the last release() call the transaction is automatically returned to the memory manager and can be reused. HTH
  12. I'm running into issues while installing SystemC using gcc version 6.2 gcc version 5.2.2 goes through fine. Running this command: I'm attaching config.log file. config.log
  13. In systems where a target can send an early response, such as a posted write, and the initiator can change the transaction after it receives the response, how do most developers handle the transaction in the target while avoiding seeing the initiator's changes to that transaction? An obvious solution is for the target to do a deep copy of the transaction, but in a complex system with many modules, having each module potentially create its own copy of each transaction can make debug and performance analysis difficult. Another option is for the target to save the relevant information from the transaction in an extension when the target receives that transaction, but this has the problem that the developers of the target must always remember to use the accessors in the extension, rather than the standard ones for the transaction.
  14. Thank you for the responses. Sorry for the delay in my response. I'd gotten busy, and I am just now getting around to signing back in. We don't seem to be having this issue anymore. I am not sure if it because of code updates or because of a compiler upgrade. We recently switched from g++ 4.9.2 to 6.2.1, so that may have resolved the issue. The path in question is sc_fifo::read() -> sc_fifo::read(T& val_) -> sc_fifo<T>::buf_read( T& val_ ). On line 410, buf_read() returns false without setting val. None of the functions in the call chain set val, so when the original call to sc_fifo::read() returns, it is returning its locally-declared tmp variable, which was passed to sc_fifo::read(T& val), which never sets val. As I mentioned, though, this doesn't seem to be causing a problem for us at the moment. It may have been a compiler issue that got resolved when we upgraded. Thank You and Regards, Patrick
  15. Well, the timer_tb gets a SC_THREAD which has exactly your sequence of writing to START and advancing time. The only difference is to use wait() instead of sc_start()...
  16. Hi All Is SystemC-Verification (SCV) useful for analog circuits(SystemC-AMS) ? or Do we have to use CRAVE?
  17. Thanks @Eyck, that did the trick. For future reference, I will put here my whole solution for LT TLM2.0 for writing and reading floating values. Normal TLM2.0 transport - write : // Normal TLM transport interface. for (unsigned int i = 0; i != 24; ++i) { unsigned int data_length = 4; unsigned int addr = rand() % 200; tlm_command cmd = i < 20 ? TLM_WRITE_COMMAND : TLM_READ_COMMAND; std::string msg = cmd == TLM_WRITE_COMMAND ? "Write " : "Read "; //OK, so whene you you want to write with regular mode into array, you should know that float value is 4 byte //and unsigned char is 1 byte. To be able to write float to unsigned char array, you must cast unsigned char array //to char array. float* buf_fl = reinterpret_cast<float*>(buf); buf_fl[0]=555.23; pl.set_command ( TLM_WRITE_COMMAND ); pl.set_address ( 8 );//targeting ram[2] pl.set_data_ptr (buf ); pl.set_data_length ( 4 ); pl.set_response_status ( TLM_INCOMPLETE_RESPONSE ); isoc->b_transport(pl, offset); buf_fl[0]=777.23; pl.set_command ( TLM_WRITE_COMMAND ); pl.set_address ( 20 );//targeting ram[5] pl.set_data_ptr (buf ); pl.set_data_length ( 4 ); pl.set_response_status ( TLM_INCOMPLETE_RESPONSE ); isoc->b_transport(pl, offset); buf_fl[0]=654.321; pl.set_command ( TLM_WRITE_COMMAND ); pl.set_address ( 796 );//targeting ram[199] pl.set_data_ptr (buf ); pl.set_data_length ( 4 ); pl.set_response_status ( TLM_INCOMPLETE_RESPONSE ); isoc->b_transport(pl, offset); Normal TLM2.0 transport - read: isoc->transport_dbg(dbg_pl); msg = " RAM at time " + sc_time_stamp().to_string(); msg += "\n"; unsigned char *moj_p; moj_p = dbg_pl.get_data_ptr(); float* moj_p_fl = reinterpret_cast<float*>(moj_p); std::cout << "it was written: "<<std::endl; std::cout<<"teting location 2 and 199: "<<moj_p_fl[2]<<" "<<moj_p_fl[199]<<std::endl;
  18. Earlier
  19. sim_input.h:344 and sim_sync.h:29 points to your code and the issue reported from sc_spawn_object is very likely caused via inlining from your Tasker::MethodFunction<> class. So you will need to look into your code to address these particular reports. For SystemC 2.3.1, the are some known Valgrind reports, most of which should have been addressed in SystemC 2.3.3. Greetings from Duisburg, Philipp
  20. Hi I am trying to understand whileBoxElement in IP-XACT and its usage. Can someone explain this and provide some examples. Thanks
  21. Hi, I am running valgrind on my application which is using SystemC library(2.3.1). I see multiple erors reported from SystemC library. Most of it looks like below:- Invalid write of size 4 by 0x2C165306: void InputInterface<cwr2rrh_t, 56u>::get<cwr2rrh_write>(cwr2rrh_write&) (sim_input.h:344) Use of uninitialised value of size 8 xxxxx::Event::await() const (sim_sync.h:29) Invalid read of size 4 by 0x2BA6C525: sc_core::sc_spawn_object<Tasker::MethodFunction<CropCOMP> >::semantics() (sc_spawn.h:83) Did anyone noticed it before? Is there any changes added in the library to suppress these valgrind errors? Any inputs are highly appreciated. Thanks in advance.
  22. Hi Erwin If I am correct, even in 1685-2009 we can describe RTL and TLM within the same component using two different views. Am I correct ? I have a scenario where I have an RTL IP with an optional port which is only present in one view(e.g. simulation view). can I use two view in such case and use viewnameref with that optional port ? Why I need to explicitly specify the typeName with wireTypeDef. In this specific case I want to use native types even when I have optional ports. Is it intentional to have typename mandatory ? How to manage two different businterfaces then ? I have an AHB bus in RTL and TLM2 bus in TLM. Do I need to describe both businterfaces in IP-Xact ? Thanks Khushi
  23. @EyckThanks for your input, the main issue for me was the sensitivity list, I just removed it from the sc_main and it works. And about defining the stimuli in a separated file, how can i achieve this if the stimuli make call to sc_start() periodically? The code is as follow, it works well, just want to know how to move the stimuli apart in a separated file int sc_main(int argc, char* argv[]) { // stimuli sc_signal<bool> START, TIMEOUT; sc_time clkPrd(10, SC_NS);// period sc_clock CLOCK("clock", clkPrd); // timer // Binding timer tm("timer"); tm.clock(CLOCK); tm.start(START); tm.timeout(TIMEOUT); // tracing sc_trace_file *tf = sc_create_vcd_trace_file("RESULT.vcd"); tm.trace(tf); // 3 cycles delay ---> first time START.write(1); sc_start(3*clkPrd); // start counting ---> first time START.write(0); sc_start(3*clkPrd); // reset before count reaches 0; 3 cycles delay ---> first time START.write(1); sc_start(3*clkPrd); // start counting again until count = 0 START.write(0); sc_start(5*clkPrd); // reset after count = 0; 3 cycles delay START.write(1); sc_start(3*clkPrd); // start counting ---> second time START.write(0); sc_start(3*clkPrd); // reset before count reaches 0 ---> second time START.write(1); sc_start(1*clkPrd); // start counting again until count = 0 ---> second time START.write(0); sc_start(6*clkPrd); // reset after count = 0; 3 cycles delay ---> second time START.write(1); sc_start(3*clkPrd); sc_close_vcd_trace_file(tf); return(0); }
  24. Thank you so much, I will working hard on your example.
  25. There is no such thing as CPU TLM modeling. Usually you write a C/C++ processor model with the needed accuracy (instruction accurate, cycle approximate, cycle accurate) and wrap it in a way that you translate memory accesses into TLM socket accesses. Along with that you need to manage to syncronization of the time of your model and the SystemC time (to run e.g. in loosly timed mode). Another task is to take the returned execution time of the bus accesses into account for the execution of the CPU model. This involves also the selection and implementation of the accesses (DMI & blocking or non-blocking). You can find a complete example of an instruction accurate VP at https://git.minres.com/DVCon2018/RISCV-VP (or https://git.minres.com/VP/RISCV-VP which is a newer version). The wrapper for the C++ model in SystemC can be found at https://git.minres.com/DVCon2018/RISCV-VP/src/branch/develop/riscv.sc/incl/sysc/core_complex.h To put it straight: doing this correctly is a non-trivial task as it is the implementation of a micro-architecture model of a CPU. One option is to build an instruction accurate ISS and add a microarchitecture model like it is done in the ESECS project (https://github.com/MIPS/esesc) BR
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