Jump to content

UVM Simulator Specific Issues

Use this forum to discuss tool-specific usage and flow issues.

Followers 7

175 topics in this forum

  1. UVM 1.1d Compatibility with Different Simulators

    By psp127143,
    • 2 replies
    • 1.2k views

  2. Problem about uvm_object_defines.svh ???

    By Guest miaoziming,   
    • 1 reply
    • 1.2k views

  3. Request: Speech Recognition for Coding(UVM/Systemverilog) and Tool GUI controls

    By chip_maker,   
    • 0 replies
    • 1.2k views

  4. RivieraPro asim assertaction:on|off syntax

    By c4brian,
    • 3 replies
    • 1.2k views

  5. TCL in RivieraPro

    By c4brian,
    • 1 reply
    • 1.2k views

  6. Questasim 10.0b errors?

    By swapnilm,
    • 0 replies
    • 1.2k views

  7. How can I record the transaction of UVM by irun?

    By u24c02,
    • 0 replies
    • 1.2k views

  8. Semantics of $past 'expression2' argument

    By tudor.timi,
    • 0 replies
    • 1.1k views

  9. does Synopsys VCS2011.03 support uvm 1.1c library?

    By mrforever,
    • 1 reply
    • 1.1k views

  10. hello world example errors??

    By swapnilm,
    • 2 replies
    • 1.1k views

  11. UVM 1.1d in QuestaSim with -pedanticerrors

    By tudor.timi,
    • 1 reply
    • 1.1k views

  12. UVM-Connect 2.3.0 Example Not Compiling for me

    By mingchu,   
    • 0 replies
    • 1k views

  13. How do I make multiple burst on systemverilog?

    By u24c02,
    • 0 replies
    • 958 views

  14. Unrecognized system task or function: $cdn_ahb_access

    By u24c02,
    • 2 replies
    • 944 views

  15. RivieraPro close single file in editor window

    By c4brian,
    • 1 reply
    • 930 views

  16. unexpected behavior of incisiv with disable in for loop

    By shubham_dce,   
    • 2 replies
    • 880 views

  17. RivieraPro tip: how to display wall-clock sim time

    By c4brian,
    • 0 replies
    • 828 views

  18. How can I dump waveform using irun uder UVM environment?

    By u24c02,
    • 0 replies
    • 614 views

  19. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02,
    • 0 replies
    • 525 views

  20. UVM-ML connecting SystemC ports

    By Khushi,
    • 0 replies
    • 444 views

  21. VCS run option to use random seed?

    By ljepson74,
    • 2 replies
    • 428 views

  22. VCS 2019.06 strong and weak support

    By ljepson74,
    • 4 replies
    • 352 views

  23. Changes in generic paylod are not reflected in UVM side

    By Khushi,
    • 0 replies
    • 331 views

  24. savl

    By SVv,
    • 2 replies
    • 280 views

  25. uvm hdl force and simulator optimization

    By wwen,
    • 0 replies
    • 269 views
×
×
  • Create New...