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  2. In IP-Xact there is a section localMemoryMap inside address space which looks similar to the memoryMap. I am not sure to understand the difference between the two and what should be used and when. Can you help me on this ? Also in IP-xact, is it possible to define a register somewhere and instantiate it or use it at other places ? Thanks Khushi
  3. Hi I have a set of registers which can be accessed from two different addr maps (uvm_reg_map) and both sees these addresses at different address. We are trying to generate such uvm registers through IP-Xact. In IP-Xact I can specify registers/register blocks but I am not sure how to specify the fact that one register/register block can be seen at different address via different map/interface. How I can specify the uvm_reg_map in IP-Xact ? Any clue/example help on this please ? Thanks Khushi
  4. Last week
  5. Compiled the systemC libraries by configuring --enable-pthreads, but same observation as before. It is in the thread's loop only. Found a link which is saying even we configure for pthread, SystemC only run threads one by one no matter how you configure your SystemC to use pthread or Window native thread. https://stackoverflow.com/questions/18646936/will-sc-thread-in-systemc-create-a-real-thread So, how can we use systemC for a simulation like this kind of use case?
  6. Earlier
  7. Hi David, I am seeing an option for enabling posix pthread for the creation of SC_THREAD. What is your opinion on the same to get the context switch without a wait method? Can you please reply with what all differences --enable-pthreads will make in SC_THREAD, SC_CTHREAD, SC_METHOD internal implementation. Thank you, Jomon
  8. Could you please explain what you mean saying 'verify register file content through assertion'. What is 'register file content'? Assertions are used to verify dynamic behavior. What you are sayying sounds static.
  9. Version 1.0.0


    Matchlib: A New Open-source Library to Enable Efficient Use of High Level Synthesis Stuart Swan Platform Architect Mentor, A Siemens Business stuart_swan@mentor.com Matchlib is a new open-source SystemC library developed by NVidia Research to enable digital hardware to be accurately and efficiently designed and verified at a high level of abstraction, leveraging commercial high level synthesis tools. Some of the key goals of Matchlib are to provide a highly configurable library of HW components that can be directly synthesized to HW with very high quality of res
  10. Hi, I'm new to systemC AMS and I want to implement statistics_config class in my project. Where can I learn more about its member functions? Couldn't find it in the user guide or elsewhere.
  11. Note/Clarification: With VCS 2019.06 and Riviera Pro 2020.04, the code in the original post works as I expected. cg_fa[0] - Coverage=78.12 % cg_fa[1] - Coverage=1.56 % I try to write code which has "universal" support across "all" simulators. Is the difference across simulators due to ambiguity in the LRM? Is some aspect of my code using a poor style? How can this code be improved for more universal simulator support? (I am trying to avoid publically contrasting simulators, which afaik is verboten.)
  12. In the LRM, it is stated that these example should not be considered as an assignment-like context: - a static cast - a default correspondence between an expression in an assignment pattern and a field or element in a data object or data value What is the consequence of this statement? Especially, what is the difference between the default correspondence (as a non-assignment-like context) and the nondefault correspondence (as an assignment-like context)? Thanks a lot Thomas
  13. I want to verify register file content through assertion in bind module , In bind statement I use : target_module bind_target_instance bind_instansiation (.*); to include all target module scope contents but when I searched for what should be the translation of that be in the bind module, I find an example for a FIFO module in the example the bind module translate all input ,output and internal vectors and signals to input to the bind module but he no information about the memory array was included , how can we access the memory or register file contents if we want to check s
  14. These terms are different. A virtual sequence defines how the local/agent sequences should behave. A virtual sequence contains sequences of different types/inheritence. The sequence library allows you to add sequences of the same type/inheritence to it. Then you can start the sequence library like a single sequence and all the sequences belonging to it will be executed in a certaim order, defind by the specified execution mechanism.
  15. What is the difference between "uvm sequence library" and "virtual sequence" ? Are these same in usage or different ?
  16. Thanks for your response. We need to simulate a processor in which the ISR will be invoked even though the FW code is in an infinite loop. Even if we call wait in FW_main, the correct functionality what an interrupt controller is capable of will not be achieved. So I may need to look for something else.
  17. Hello @Beginner_KOR, I would recommend going through details on SystemC TLM modeling using the following resources in no particular order: SystemC Standard document: IEEE 1666-2011(Must read) SystemC from Ground Up 2nd Edition by @David Black. https://github.com/dcblack/SCFTGU_BOOK/ Looking at SystemC TLM examples in the SystemC Sources: https://github.com/accellera-official/systemc/tree/master/examples/tlm SystemC TLM-2.0 examples on EDA Playground: https://www.edaplayground.com/playgrounds?searchString=&language=C%2B%2B+only&
  18. In a cooperative multitasking environment (e.g. SystemC), it is impossible to have an infinite loop without yielding. The only yielding method available in SystemC threads is the wait() method; therefore, you have self-defined an impossible problem. SystemC processes (SC_THREAD and SC_METHOD) are NOT the same concept as OS processes or threads. They are constructs of the discrete event driven simulator known as SystemC. Now it is possible in some cases to trick the code, which I have used for some cases. For example, if your FW_main code where to attempt some I/O with a common method
  19. Be very careful with terminology here. If you are asking about host simulator OS threads, the answer is pretty much no. SystemC is a discrete event driven simulator using cooperative multitasking (which greatly simplifies coding) and is not thread safe. You might want to look at what is contributing to the slowdown. You should probably use a software profiler. There are two issues that commonly cause problems in SystemC: I/O. More specifically output to the log file. If your simulation has lots of SC_REPORT_INFO or std::cout producing large logs at run-time, then you will defin
  20. I'm working on an app simulating a system on a chip with a few dozen SC modules. Its wall clock run time is too long, and with planned new functionality will take even longer. So I'm looking for ways to improve performance. E.g. currently the application is currently running as a single O/S thread, is there a way to make each module run in its own O/S thread? Many thanks!
  21. I am on the implementation of an interrupt controller simulator, which will take signals from other rest of the HW modules in simulation and run the ISR. Below is the systemC code roughly made to get the concept clear. In this case, we need ISR to be handled in a way that, even if the FW_main is stuck inside while(1) loop. With the below implementation the context is inside FW_main loop only. Adding a wait in FW_main is not the one we want. We need the correct interrupt controller functionality. Any ideas to get rid of this problem? Please share your inputs. Thanks in advance.
  22. HI, I'm just starting to learn systemC TLM modeling, however it's not easy to understand. I'm trying to searching any good TLM example but would you let me know any good example for simple write/read control system based on APB or AHB? If there is, it will be great for a beginner like me.
  23. Hello @berry_runner, Regarding a dedicated training look here: https://www.doulos.com/training/ But as a starter in this, I would recommend getting to know following in no particular order: C++11/14/17: Useful for writing concise and clean code. SystemC from Ground Up 2nd Edition by @David Black. https://github.com/dcblack/SCFTGU_BOOK/ Look into the examples directory in SystemC sources. https://github.com/accellera-official/systemc/tree/master/examples Look into publicly released projects on Github: https://github.com/topics/systemc
  24. Hi, I'm taking a SystemC course right now for my graduate program, and I am seeking additional help beyond what my TA's can provide me. Are there any recommended tutors or places where I could find tutors?
  25. Hi, I am trying to port my uvm code from UVM 1.1d to UVM-IEEE. Having the following line in my code: `uvm_field_queue_object(p_ext_agents, UVM_ALL_ON | UVM_REFERENCE) where uvm_component p_ext_agents[$]; cause the following compile error: `uvm_field_queue_object(p_ext_agents, UVM_ALL_ON | UVM_REFERENCE) | xmvlog: *E,DBITNS (sia/lib/sv/cdn_iwb/sv/cdn_iwb_routing_model.sv,172|98): The argument of the system function call was not of bit-st
  26. And I apologize for the late answers but email notifications was turned off. Now they are turned back on.... /JSA
  27. Some comments/answers.... @Thomas T: Adding a uvm_fatal in the constructor is of course possible but the compilers should catch it. Some do and some don't. I do not see this a s a big issue. When we toss backwards compatibility then it can be turned into an abstract class now as UVM IEEE should support this in the factory. More examples are always nice 🙂 The scoreboard is delivered as an end-point you can say. All the infrastructure leading upto the scoreboard is your own responsibility.. Now, you are right that you need a component which basically does a type cast on the AP in
  28. Thanks for your response and advice. It is not a full test bench, it is only a test case to demo the issue. As i mentioned at the first line of code // skipped driver and others. `uvm_declare_p_sequencer(xx) is a leftover for my debugging, it should not be there, but it has no effects anyway. The issue is from below while-loop function void uvm_sequencer_base::stop_sequences(); uvm_sequence_base seq_ptr; seq_ptr = m_find_sequence(-1); while (seq_ptr != null) begin kill_sequence(seq_ptr); seq_ptr = m_find_sequence(-1); end endfunction I wo
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