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  2. This question is NOT a question for Accellera since Questa is a product of Mentor Graphics. Due to legal requirements it would NOT be appropriate for anybody to respond to your question here except to tell you to go elsewhere. You may read the preceding thread for a few clues, but if that does not suffice then please redirect your questions to Mentor.
  3. I was reading Accellera's "uvm_users_guide_1.2" and found this: Mirroring Unmapped Registers When using explicit or passive monitoring to update the mirror value in unmapped registers, it will be necessary to override the uvm_reg::predict() method of the register(s) used to access the unmapped registers, since the observed transactions will be using the address of those access registers, not the unmapped (unaddressable) registers that are ultimately accessed. So I think if I am able to override the predict method of my unmapped registers, then I will be able to mirror their values correctly. However, I don't know how to override the predict method of a register. Could anyone teach me how? Thanks!
  4. Last week
  5. Silly me, I was quite mistaken in my simple solution (and it only took me a few minutes after posting to realize it); however, this exercise reminded me of a 2011 feature: reset. This works for SC_METHOD processes, but is inconvenient for SC_THREADs. I enjoyed working the puzzle. You can see a full working example here: https://www.edaplayground.com/x/39QM Outline: When registering your SC_METHOD process capture the process handle and specify dont_initialize(). At the start of your method implementation, check for the trigger state of reset_event and return immediately if triggered. To reset static sensitivity, simply issue reset on the process. Include a comment that you are simply interrupting. Note 1: This assumes you are using a version of SystemC 2.3.3 or later. If using 2.3, you will need to add a bool flag that is set at the time of invoking reset and cleared inside the process upon detection. Note 2: You could also use reset_signal_is(); however, that would require adding deassertion and would be messier in my opinion. An alternate and less intrusive method would be to simply add an interrupt event into the sc_event_or_list every time you change sensitivity: next_trigger(some_event | interrupt_event); next_trigger(time_delay, interrupt_event); Unfortunately, this doesn't work for sc_event_and_list; however, you can synthesize that situation with another process. I will leave that for you to figure out.
  6. You can restore a process' sensitivity only while executing the process prior to yielding. If that is the case, simply invoke next_trigger(void). Once you have yielded (returned), you will have to wait until you are triggered. If you don't call next_trigger() at all inside your method, then static sensitivity is implied for the next invocation. Static sensitivity is really just a precompiled list of of or conditions and is not really different from dynamic sensitivity anyhow. It is called static because it is established prior to the start of simulation (normally during construction). For dynamic processes, it concept is similar, but the "static" list is established prior to sc_spawn. So a simple solution is to add an event designed to get your waiting SC_METHOD back to reset the sensitivity. This can be done with 1 sc_event and a bool. I will illustrate in a followup post.
  7. Hello everyone, I want to restore a triggered SC_METHOD process to its static sensitivity at immediate notification once some conditions qualify. We can use sc_trigger() to restore its sensitivity to static but in my case it won't help. I will elaborate the situation here, assume process A is been triggered to execute at time 't' after 'now', but in between the 't' and 'now', some conditions wants process A to restore it to its static sensitivity and my question is how to do it? Thanks!
  8. UVM-SystemC 1.0-beta3 was released for public review. Download available at https://www.accellera.org/downloads/drafts-review. Notable changes since 1.0-beta2: Register API Bugfixes & SystemC 2.3.3 support Ubus example Automatic objection mechanism
  9. You do not say anything about a relationship between interface A and B, i.e. can you do a few transactions on the cmd interface without needing the data from the data interface or vice versa. Please elaborate.
  10. Earlier
  11. I have DUT interface with A,B (list of singals) that needs to be driven with some timing dependency . A is cmd interface ,B is data interface . Now i plan to implement driver should i have separate sequence from signals list A and signals list B . If so how would i synchronize two sequences sequences so that i meet the timing relation between these two . Or should i have implemeted both cmd and data in same sequence item and have the logic in driver so it driver cmd and data after timing is meet . I dont like this approach as i need fill my driver with timing code . I want my timing information to be in sequence .
  12. Dear TLM Experts, Could someone please shed some light on this ? I have been able to create a transactionID using extension in GP. In order to trace how each transaction is progressing in my system, I am thinking of using transport_dbg API of sockets, such that every time a socket sends or receives a Tx - it will get logged. Would this be right / clean way of logging every Tx ? I am not clear yet about who would call transport_dbg (with in socket class) after I register a callback for transport_dbg ? Also when is transport_dbg called when Tx travels via non blocking interfaces of an initiator or target sockets ? Thanks.
  13. Yes, many publications have been posted on this during the last decade. Check IEEEEXplore for the papers. Another approach is check publications from DOCEA POWER, a company which was focusing on this, and is still active in this domain (although under a different name)
  14. Hi everyone, I want to ask can we use systemc for power modelling if can, pls share some link that provide information and tutorial about it. Thak you.
  15. Hi All Basically for debugging purpose I want to trace every transaction (Tx) going around in my model. I would like to assign an ID to each Tx so that it becomes easy to trace them. I have following questions in this context. I am in early stages of using TLM . 1. What is best way to annotate each Tx ? a) I am thinking of using extensions in generic payload - following ./tlm-2/examples/lock_example.cpp b) Could there be some generic TLM classes in open source that people developed for this specific purpose ? I am thinking of wrappers around core gp, and enhanced sockets classes which could facilitate monitoring and logging of Tx using IDs. 2. What is best way to switch between debug and release version - wherein debug version each Tx is traced ? I guess, like 1.b, I am again asking if you know of open source wrapper classes which can facilitate this in run time ? Thanks.
  16. For ordinary memory transfers, you want the data length equal to the streaming width. For FIFO-like transfers, you would set the streaming width to the width of the FIFO, which will be less than the data length. Having a streaming length greater than the data length is somewhat pointless; however, it you don't want to think about it, using a value of UNINT_MAX (#include <climits>) is a great way of ensuring that streaming won't mess up the transaction. The default constructed value of streaming width is zero and illegal.
  17. Hi SC/TLM experts, I have same question/need. Could someone please enlighten ? Are there examples which illustrates usage of gp extensions ? Thanks.
  18. Hi Eyck, Thanks for your replay and help. Will reach out. Thanks.
  19. You may check section 14.12 Data length attribute and '14.15 Streaming width attribute' in the LRM. The first says: while the second states in paragraph 😄
  20. @ljepson74, All you have to do is import uvm_pkg::uvm_enum_wrapper; and you've got this handy little class to use, you don't even need to have a class based testbench.
  21. @uwes, thank you. For better or worse, the project that I work on for this does not use UVM. (Yes, I realize that this is a UVM forum and that my question is just a vanilla SV one.) I'll keep this response you sent in mind for the future and look forward to trying it. That looks like a clear and terse solution - which is what I look for. (Hopefully my next project uses UVM.) @chr_sue, Thanks. But what I try to do is the reverse. i.e. to see if the value of my_string (which is of type string) is one of the my_enum states. So, using the cast style you show, I'd need to cast each state of my_enum to string, and then compare it. As it is, I can just do a direct compare to see if there is a match, without any cast. Thank you, though. You got me thinking about this differently. For now, I just walk thru my_enum and check each state for a match with my_string, to see if my_string has a legal value. (To provide some more details, I am checking that a command-line input plusarg string is of a legal value for the test. The legal values are stored as an enum. Storing them as an enum allows them to be used elsewhere; as opposed to just having an array of legal string values.)
  22. Your questions are answered by clause "Function sc_start" in IEEE Std 1666-2011: More details on the simulation cycle, you can find in clause 4.2 "Simulation". Yes, see clause of IEEE Std 1666-2011: Clause 4.5.7 of IEEE Std 1666-2011 lists functions to detect pending activity: sc_pending_activity_at_current_time(), sc_pending_activity_at_future_time(), sc_pending_activity(), and sc_time_to_pending_activity().
  23. I have a processor-like construction, and the execution time is simulated in the model using wait(time), i.e. I indend to provide the simulated execution time as argument of sc_start(), to imitate step-wise execution. Can I be sure, that in the model, the simulation will stop 'after' executing the simulated instruction; that is, reaching limiting time will terminate execution at the very end of the delta cycle? The other possibility that timeout is only one of the events, and by chance, it can be NOT the last. BTW: as I understood, a second sc_start() will continue simulation "as it was", i.e. it makes no initialisation, uses no maybe forgotten temporary variables, etc. It is correct? BTW2: How can I find out (at the last instruction) that the simulation finished (no more events left in the engine), and no use to issue another sc_start()?
  24. Verbosity has already been processed before you get to the report catcher. https://accellera.mantishub.io/view.php?id=7211
  25. Does anybody know how the set_verbosity works inside the uvm_report_catcher. As I understand default verbosity is UVM_MEDIUM hence I set the verbosity to UVM_HIGH so the message wont get displayed. Looks like the message is still getting printed on the logfile, another workaround is to use set_action(UVM_NO_ACTION). but what shld be the correct value to set in the set_verbosity("") so that it wont display on the logfile. Example here: edaplayground.com/x/4T8p
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