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  1. Yesterday
  2. Hi Kushi, The additional system interfaces allow you to make (clock, reset, sideband) connections in addition to the master/slave connections. So you can separately handle your clock/reset/sideband connectivity. The system group names are not relevant for netlisting. They provide additional checking capabilities in IP-XACT. Best regards, Erwin
  3. Hi Kushi, As I mentioned earlier ( https://forums.accellera.org/topic/6446-interface-mode-mirroredmaster-mirroredslave/ ) my advice is to map clock and reset signals in interfaces. However, this is an advice. Other ways of working are to handle clock and reset with adhoc connections or dedicated clock and reset bus interfaces. The IP-XACT standard does not enforce a particular way of working. The official AMBA bus definitions contain clock and reset in master and slave interfaces. They are optional to allow people to decide for themselves whether they want to map clock and reset in those interfaces. In my environment, we choose to make those signals required because we want to enforce a certain way of working. Best regards, Erwin
  4. Hi Kushi, Clock and reset have direction in because that is the direction from the protocol point of view. Clock and reset signals are generated by clock and reset generators. If you map clock and reset in your master and slave bus interfaces, you need to drive the clock and reset signals. You can do this by inserting a so-called phantom component on the interconnection. A phantom component is a component that only has phantom ports (ports with direction phantom). Here is an example with clock only: Component A with input port clk mapped in AMBA master bus interface m Component B with input port clk mapped in AMBA slave bus interface s Design with instance a of component A and instance b of component B and interconnection from a.m to b.s If you netlist the design you will a get a net between a.clk and b.clk but this net is not driven since both ends of the net are inputs. Now lets assume you also have Component C (clock generator) with output port clk mapped in CLOCK master bus interface clock. As integrator, you can now make an integration specific phantom component and change the design as follows: Component I with phantom port clk that is mapped in three three bus interfaces CLOCK slave bus interface clock AMBA slave bus interface s AMBA master bus interface m Design as before with the interconnection and additional instance c of Component C and instance i of Component I and interconnections a.m to i.s i.m to b.s c.clock to i.clock If you now netlist this design you will get a net between c.clk (driver) and a.clk and b.clk. Instance i will not appear in the netlist as a module instance since it only has phantom ports. In my opinion, the use of a phantom component is the cleanest way to do this. Alternative ways are to connect c.clk via an adhoc connection to a.clk and/or b.clk, or to add additional clock slave interfaces to A or B such that you can connect c.clock to those interfaces. However, you then add additional interfaces only for integration purposes. There is an example in the user guide ( https://accellera.org/images/downloads/standards/ip-xact/IP-XACT_User_Guide_2018-02-16.pdf ) of a phantom component for I2S. You can make similar components for AMBA protocols and other Serial protocols. Best regards, Erwin
  5. Thanks Erwin for the nice explanation. I have an additional question here. As you mentioned system interfaces are used to connect clock, reset and sidebands signals. How the system interfaces are helpful to connect these ? Are they provide some extra capabilities which is not there if we use normal(master/slave) interface connections or adhoc connections. How the system group name in busdefs for the system bus interfaces are used in net-listing. Thanks Khushi
  6. Last week
  7. Thanks Erwin for the detail explanation. In almost all protocols we have clk and rst signals which are "in" on both master and slave. So does it mean for all such protocols the corresponding bus interface in component should be always mirroredSlave(instead of master) and mirroredMaster(instead of slave) Or we should not map clk and reset in component bus interface and keep them as master or slave (instead of mirroredSlave or mirroredMaster) Thanks Khushi
  8. Hello I am referring to selction 5.13 Clock and reset handling in IEEE 1685-2009. With this I have few questions. I have a bus protocol for which I need to create a busdef/absdef pair. For example lets say I am creating AXI busdef/absdef pair. In my component I have an AXI master and a AXI slave interface. The clock and reset for both the interfaces have common driver. In this context, I am not sure - if I should list clock and reset in corresponding absdef or not. If yes should I leave them un-mapped in corresponding bus interface in component so that these are not connected when I connect this bus interface to other side ? - in the component IP-Xact should I create a separate bus inteface for reset and clock ? In general almost all protocols are dependents on clock and reset. In this case what are the general guidelines and recommended ways for clock and reset handling. Thanks Khushi
  9. Hi Kushi, A system bus interface must be connected to a mirrored system bus interface. Sometimes, system interfaces are used to connect clock and reset signals or side-band signals. An EDA tool behaves the same for system interfaces as for master/slave interfaces. It maps component ports onto logical ports, wires the logical port bits, and infers from that which ports from which component instances need to be wired in a generated netlist. There is no addressing associated with system interfaces. Personally, I do no use system interfaces. In my opinion, the better approach is to map clock and reset in master and slave interfaces. This allows the use of abstractors to bridge between RTL and TLM descriptions. Clock and reset are needed at the RTL side but they are abstracted at the TLM side. This is not possible with system interfaces. In general, to enable IP re-use, i.e. in IP-XACT terms to enable IP-XACT component reuse, an IP-XACT component shall not have bus interfaces specifically tailored to way the IP-XACT component is integrated in its context. I think this is a good way of thinking while creating IP-XACT components. Best regards, Erwin
  10. Hi Kushi, In an abstraction definition, you can describe the properties of logical ports for master, slave, and system interface. For wire ports, the properties are presence, width, and direction. In a bus interface, the component ports mapped onto the logical ports have to obey the semantic consistency rules concerning the directions (SCR 6.* in IEEE 1685-2014). For instance, SCR 6.5, a logical port with direction in can only be mapped onto a component port with direction in, inout, or phantom. For a mirrored bus interface, the direction of the logical port must be reversed. If an abstraction definition contains logical ports such that for each logical port the direction in a master is mirrored compared to the direction in a slave, and also presence and width are identical in a master and a slave, then from the netlisting point of view there is no difference between a master interface and a mirrored slave interface and also no difference between a slave interface and mirrored master interface. Such an abstraction definition is sometimes called symmetric. However, if an abstraction definition is asymmetric, then SCRs 6.* imposes different constraints for master/mirrored slave interfaces and slave/mirrored master interfaces. A typical example is a logical clock port (see all AMBA bus definitions). The logical ports PCLK, HCLK, and ACLK have direction in for master and slave interfaces. Another example is IEEE 1149.1 JTAG (see https://www.accellera.org/images/busdefs/busdef_SpiritCons_Accellera_1685-2009_final.zip) where logical ports TDI and TDO have a width of 1 in slave interfaces and no width in master interfaces. As a result you can mapped multiple TDI/TDO bits in a mirrored master interface but only 1 bit in a slave interface. The use of mirrored and non-mirrored interfaces is not only relevant for connectivity but also for internal addressing in a component. If you use mirrored interfaces then the internal addressing can only be expressed using channels (from mirrored master to mirrored slave). If you use non-mirrored interfaces then the internal addressing can only be expressed using bridges (from slave to master). It is not possible to describe internal addressing with a combination of mirrored and non-mirrored interfaces (e.g. addressing from a mirroredMaster to a master). As a result, it is not possible to cascade components that use channels for addressing. Hence, my advice is always to use bridges for addressing in combination with non-mirrored interfaces. In my opinion, the use of mirrored interfaces only makes sense in combination with non-addressable bus definitions that are asymmetric. Typically, these are serial protocols such as JTAG, but also I2C, I2S, SPI, and so on. Often they have an output enable logical port with direction out for master and slave interfaces. In that case, you functional IO muxing component needs mirrored master and slave interface to allow the output enable signal to be input. Please see the above referenced accellera.org bus definitions. Best regards, Erwin
  11. Are you using a commercial simulator for your setup? Then consult its manual; but typically, you can use "-D<macro>[=<value>]" to define a macro.
  12. You could use an optional command line parameter to sc_main and propagate that to the "real" test.
  13. -runcmd_args+="DPI_CFLAGS+=-DHASH_DEFINE_VAL=1" does not update or pass on any value change to the define where "HASH_DEFINE_VAL" is a #define in one of the headerfiles that are compiled. Is there a way this can be done? Thank You
  14. Hi would like to call a UVM SystemC test inside another UVM systemC test. While doing so, I would like to pass a parameter to the first test so that it uses that value an accordingly runs the test, and if I do not so so, I would like it to take a default value and continue on with the build, run phase etc. Is it possible to do so ? If so how would I do it? Thank You
  15. The register adapter contains 2 functions: (1) bus2reg (2) reg2bus bus2reg implements the path from the pinlevel interface to the register layer. This is the path which returns the rD-data (ahb_hrdata). reg2bus implements the path from the register layer to the pimlevel interface. This is the path which is used to send the WR-data ahb_hwdata) from the register layer to the DUT.
  16. I believe registerFile concept in IP-Xact can handle the 2 dimensional registers as Ankit specified above.
  17. Hi When we should use system businterface in IP-Xact and how an EDA behaves when it sees system businterface vs master/slave ? Thanks Khushi
  18. Hi Can anyone explain me when to use mirroredMaster and mirroredSlave interface mode in IP-Xact businterfaces. I am not able to understand when to use master vs mirroredSlave (or slave vs mirroredmaster). I have a set of bus protocols for which I created a set of busdef/absdef but in component I am not able to decide whether to use master vs missoredSlave and slave vs mirroredMaster. Can someone explain here in layman terms the different between master and mirroredSlave (slave vs mirroredmaster) and when to use mirror interfaces and what is the consequence in generated netlist. Thanks Khushi
  19. Hello Experts, We have implementation of AHB sequence item having hwrada as well hrdata data without any additional override sequence classes for each case. We have implemented (more properly reused what was there) the following generic adapter bus2reg implementation : virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); ahb_ivc_seq_item ahb_bus_adapter; if (!$cast(ahb_bus_adapter, bus_item)) begin `uvm_fatal("NOT_AHB_BUS_ADAPTER_TYPE","Provided bus_item is not of the correct type") return; end rw.kind = (!ahb_bus_adapter.ahb_hwrite) ? UVM_READ : UVM_WRITE; rw.addr = ahb_bus_adapter.ahb_haddr; rw.data = ahb_bus_adapter.ahb_hrdata ; rw.n_bits = (ahb_bus_adapter.ahb_hsize == 3'b010) ? 32 : 8; rw.status = UVM_IS_OK; endfunction : bus2reg; Shouldn't there be something like : // rw.data = (!ahb_bus_adapter.ahb_hwrite) ? ahb_bus_adapter.ahb_hrdata : ahb_bus_adapter.ahb_hwdata; instead of the bold line ? As it seems to me the old peace of code was refering to case there is only one data line.. Thank you for any advice , Oleg Greenberg
  20. Doulos UVM Golden Reference Guide Kindle Edition: https://www.amazon.com/dp/B01HDQEN0Q/ref=cm_sw_em_r_mt_dp_U_4YeXDb7QW80NC
  21. Hi John, Is an ebook version of UVM GRG available? Best regards, Anand
  22. Looks like XY problem to me. If you need pointer to event, use pointer.
  23. Interesting, I'm not an expert in CMake, but even with existing CMakeLists.txt when I build my application SystemC include directory is recognized automatically as system headers: And as a result I don't receive any warnings about issues in SystemC headers.
  24. You forgot ";" here: using namespace std;
  25. Hello Everyone, I have just started to learn system C and I have installed the 2.3.3 version on my linux system 18.04. I have tried installing in usr/local as well as in the local directory (for example : In the downloads itself). I have a very simple hello world program, but i have an error. I feel it is the problem with the installation, any help is highly appreciated. Thank you very much in advance. lugia@celebi:~/SystemC$ make Makefile:56: *** SYSTEMC_HOME [/usr/local/systemc-2.3.3/] is not present. Please update Makefile.config. Stop. lugia@celebi:~/SystemC$ make Makefile:56: *** SYSTEMC_HOME [/usr/local/systemc-2.3.3/] is not present. Please update Makefile.config. Stop. lugia@celebi:~/SystemC$ export SYSTEMC_HOME=/home/lugia/Downloads/systemc-2.3.3/ lugia@celebi:~/SystemC$ make g++ -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/home/lugia/Downloads/systemc-2.3.3//include -c hello.cpp -o hello.o In file included from /home/lugia/Downloads/systemc-2.3.3//include/systemc:74:0, from /home/lugia/Downloads/systemc-2.3.3//include/systemc.h:219, from hello.cpp:1: /home/lugia/Downloads/systemc-2.3.3//include/sysc/kernel/sc_module.h:397:5: error: expected ‘;’ before ‘struct’ struct user_module_name : ::sc_core::sc_module ^ hello.cpp:4:1: note: in expansion of macro ‘SC_MODULE’ SC_MODULE (hello_world) { ^~~~~~~~~ Makefile:109: recipe for target 'hello.o' failed make: *** [hello.o] Error 1 lugia@celebi:~/SystemC$ The error is as stated above. The code is as below. #include <systemc.h> using namespace std SC_MODULE (hello_world) { SC_CTOR (hello_world) { } void say_hello() { cout << "Hello World SystemC-2.3.1.\n"; } }; int sc_main(int argc, char* argv[]) { hello_world hello("HELLO"); hello.say_hello(); return(0); } and my make file is as follows SYSTEMC_HOME?=/home/lugia/Downloads/systemc-2.3.3/ TARGET_ARCH = linux64 FLAGS_COMMON = -g -Wall FLAGS_STRICT = -pedantic -Wno-long-long FLAGS_WERROR = -Werror PROJECT = hello #INCDIR = -I.\ # -I../usaTrackBusSimple OBJS = $(PROJECT).o ## default values for additional setup variables ifneq (,$(strip $(TARGET_ARCH))) ARCH_SUFFIX ?= -$(TARGET_ARCH) endif LDFLAG_RPATH ?= -Wl,-rpath= SYSTEMC_INC_DIR ?= $(SYSTEMC_HOME)/include SYSTEMC_LIB_DIR ?= $(SYSTEMC_HOME)/lib$(ARCH_SUFFIX) SYSTEMC_DEFINES ?= SYSTEMC_CXXFLAGS ?= $(FLAGS_COMMON) $(FLAGS_STRICT) $(FLAGS_WERROR) SYSTEMC_LDFLAGS ?= -L $(SYSTEMC_LIB_DIR) \ $(LDFLAG_RPATH)$(SYSTEMC_LIB_DIR) SYSTEMC_LIBS ?= -lsystemc -lm ## Add 'PTHREADS=1' to command line for a pthreads build ## (should not be needed in most cases) #ifdef PTHREADS #SYSTEMC_CXXFLAGS += -pthread -fPIC #SYSTEMC_LIBS += -lpthread #endif ## *************************************************************************** ## example defaults ## - basic configuration should be set from Makefile.config FILTER ?= cat INCDIR += -I. -I.. -I$(SYSTEMC_INC_DIR) LIBDIR += -L. -L.. CXXFLAGS += $(CFLAGS) $(SYSTEMC_CXXFLAGS) $(INCDIR) $(SYSTEMC_DEFINES) LDFLAGS += $(CFLAGS) $(SYSTEMC_CXXFLAGS) $(LIBDIR) $(SYSTEMC_LDFLAGS) LIBS += $(SYSTEMC_LIBS) $(EXTRA_LIBS) # "real" Makefile needs to set PROJECT ifeq (,$(strip $(PROJECT))) $(error PROJECT not set. Cannot build.) endif # basic check for SystemC directory ifeq (,$(wildcard $(SYSTEMC_HOME)/.)) $(error SYSTEMC_HOME [$(SYSTEMC_HOME)] is not present. \ Please update Makefile.config) endif ifeq (,$(wildcard $(SYSTEMC_INC_DIR)/systemc.h)) $(error systemc.h [$(SYSTEMC_INC_DIR)] not found. \ Please update Makefile.config) endif ifeq (,$(wildcard $(SYSTEMC_LIB_DIR)/libsystemc*)) $(error SystemC library [$(SYSTEMC_LIB_DIR)] not found. \ Please update Makefile.config) endif ## *************************************************************************** ## build rules .SUFFIXES: .cc .cpp .o .x GOLDEN?=$(firstword $(wildcard ../results/expected.log golden.log)) EXEEXT?=.x EXE := $(PROJECT)$(EXEEXT) all: announce build announce: @if test x1 = x$(FLAG_BATCH) ; then \ echo; echo "*** $(PROJECT):"; echo; \ fi check: announce all @if test -f "$(INPUT)" ; then INPUT="< $(INPUT)" ; fi ; \ eval "$(VALGRIND) ./$(EXE) $(ARGS) $${INPUT} > run.log" @cat run.log | grep -v "stopped by user" | \ $(FILTER) | awk '{if($$0!="") print $$0}' > run_trimmed.log @if test -f "$(GOLDEN)" ; then \ cat "$(GOLDEN)" | grep -v "stopped by user" | \ awk '{if($$0!="") print $$0}' > ./expected_trimmed.log ; \ diff ./run_trimmed.log ./expected_trimmed.log > diff.log 2>&1 ; \ if [ -s diff.log ]; then \ echo "***ERROR:"; cat diff.log; \ else echo "OK"; fi \ fi run: announce all @if test -f "$(INPUT)" ; then INPUT="< $(INPUT)" ; fi ; \ eval "./$(EXE) $(ARGS) $${INPUT}" build: announce $(EXE) $(EXE): $(OBJS) $(SYSTEMC_LIB_DIR)/libsystemc.a $(CXX) $(LDFLAGS) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt @test -x $@ .cpp.o: $(CXX) $(CXXFLAGS) -c $< -o $@ .cc.o: $(CXX) $(CXXFLAGS) -c $< -o $@ clean:: announce rm -f $(OBJS) $(EXE) core $(EXTRA_CLEAN) \ run.log run_trimmed.log expected_trimmed.log diff.log ultraclean: announce clean rm -f Makefile.deps *~ #Makefile.deps: # $(CXX) $(CXXFLAGS) -M $(SRCS) >> Makefile.deps #include Makefile.deps
  26. Hi, I have 2 suggestions for the current SystemC reference implementation. I started to use pandantic compiling option for my project and this throws many warnings in SystemC headers. Altough it's annoying but there many simple fixes for unused variables. For base classes where you don't use the proposed parameter like here (one random example) ../systemc-lib/src/tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h:349:57: warning: unused parameter 'ext' [-Wunused-parameter] template <typename T> void clear_extension(const T* ext) you can simply switch to this one template <typename T> void clear_extension(const T* /*ext*/) If you want I can do a pushRequest for this on github. But maybe you are not interested in this, than you could at least make it easy for users of CMake to not print them, if they compile their code. The simplest approach for this is to change the CMakelists.txt in src from ... target_include_directories(systemc PUBLIC $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}> $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>) .... to target_include_directories(systemc PRIVATE $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}> $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}> PUBLIC INTERFACE $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}> $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>) kind regards
  27. I have a class with an sc_event which should be readable and writeable through getter and setter methods. class IntWithEvent { private: sc_event _ev_wr; sc_event _ev_trigger; public: const sc_event& get_write_event() const { return _ev_wr; } const sc_event& get_trigger_event() const { return _ev_trigger; } void set_trigger_event(sc_event &ev) const { _ev_trigger = ev; // E0349 no operator "=" matches these operands } } Writing the getters was no problem. However the setter throws me an error of no matching assignment operator. Do I need to store a pointer to a sc_event and then set the pointer to the address of the parameter? It doesn't give me compile errors like this. class IntWithEvent { private: sc_event _ev_wr; sc_event *_ev_trigger; public: const sc_event& get_write_event() const { return _ev_wr; } const sc_event& get_trigger_event() const { return *_ev_trigger; } void set_trigger_event(sc_event *ev) { _ev_trigger = ev; } } I was taught to avoid pointers where I can. Is there a way to avoid the pointers?
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