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  5. Hello I started learning SystemC AMS recently, and I am getting familiar with this as it reminds me of using Matlab/Simulink (aside from having to write out my signal flow graph in code, which is fine to me). I tried playing around with LSF models for now to get more familiar. I tried to build a model representing a duffing-oscillator (https://en.wikipedia.org/wiki/Duffing_equation). Now I have trouble building the x(t)^3 term of the differential equation. As far as I understood I cannot simply apply the C++-Multiplication to sca_signal nor can I synthesize a cube (or other operation
  6. Hi Mats, As you say, you can add a special address block with a width of 128 (or more). The width indicates the maximum number of bits that can be accessed in a single transaction. This address block can contain registers with a size equal to the width or smaller. Best regards, Erwin
  7. Posting on behalf of Brent Sherman, IPSA WG Chair: Hi Everyone, On behalf of the IP Security Assurance Working Group, I'd like to welcome you to the feedback portal for the SA-EDI 1.0 Public Review. If you haven't yet downloaded the document, it is available here. In order for your voice to be heard, it is imperative that you provide your detailed feedback and questions via this forum before the end of the Public Review period, which will be May 21, 2021. We ask that you make use of the page and line numbers, as well as figure, table, syntax and example numbers/captions to make
  8. I suggest to first try launching your SystemC-AMS application under control of `gdb` from the command line to ensure seeing all error messages. My experience with IDEs is, that they sometimes do not show all relevant text of error messages making people look for the source of the problem in the wrong places.
  9. SystemC 2.3.3 and later already support QuickThreads on aarch64! Maybe you just need to update your SystemC version? If you should encounter problems on this platform, feel free to report them on this forum. Using SystemC on aarch64 is probably not yet very widespread. So, we welcome any feedback!
  10. Thanks @Guillaume Audeon for reporting the issue and proposing a possible fix! I have forwarded it to the SystemC LWG. Could you be a bit more specific, with which SystemC version you are observing the segmentation fault on CentOS 7? Did you observe it with the latest official release tar ball of SystemC 2.3.3 or with the HEAD from the official SystemC Git repository?
  11. When I build a program with systemc this Error doesn't apppear , but when I build systemc-ams I get this Error, I think this Error from Gdb because I'm using Eclipse under cygwin64
  12. You are apparently not debugging the compiled executable, but the C++ source file `main.cpp`. Check the manual of Eclipse CDT on how to configure the IDE for debugging a built program. If I remember correctly (haven't used Eclipse) for some time, it should suffice to right-click on the executable in the project navigator pane and select from the context menu "Execute and debug program" or something similar.
  13. I cannot reproduce your problem. I copied your source code to files and build it. The comparator-pdf.vcd file generated by the executable contained the following three traces for v_p, v_n, and z, which match my expectations from inspecting your code:
  14. mr.maehne I have problem when I'm trying to debug a systemc-ams programe I get this message: Error in final launch sequence: Failed to execute MI command: -file-exec-and-symbols C:/Users/ALTQNIA/eclipse-workspace/Td_BBT/src/main.cpp Error message from debugger back end: "C:/Users/ALTQNIA/eclipse-workspace/Td_BBT/src/main.cpp": not in executable format: file format not recognized Failed to execute MI command: -file-exec-and-symbols C:/Users/ALTQNIA/eclipse-workspace/Td_BBT/src/main.cpp Error message from debugger back end: "C:/Users/ALTQNIA/eclipse-workspace/T
  15. That surprises me a bit, I assumed that there would be no such "hard" requirements on virtual registers, and that that would be the motivation to have the feature to begin with. Looking at my problem from the other direction then, if I have several addressblocks inside a memorymap, the databus and the registers being 32 bit. Then there is a special addressblock that contains some wider (e.g. 128 bit, or even more) datastructures. Those are also updated over the 32 bit bus, the updates are made safe somehow, e.g. through buffered writes, or some more global synchronisation (like disable th
  16. Thanks.., Yes as you said running on a different thread does the job but there are lot many problems as you said. We need to try out the ISS as you have suggested.
  17. Hi, Thank you David and "basarts" One follow up question on this. I found that it is possible to use SYSCAN to instantiate C-models in RTL testbench and do VCS simulation. Unfortunately SYSCAN is having some issues with latest version of VCS. I am wondering if there is some way to get rid of SYSCAN and use some other method to run VCS simulation in RTL testbench with C-model instantiation. Thanks in advance. Regards, Nithin
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  19. Hi, I have one question, I have files from quick thread and copyright is Copyright (c) 1993 by David Keppel, that file is assembly file. I want to make a new port for aarch64 or be informed if it is already written by Quick Thread people. I want to compile that file(s) using aarch64-linux-gnu-g+, but get error because that is not written for aarch64 yet. here is the files attached. Thanks in advance. architecture.S architecture.hpp
  20. Hi Mats, Yes, my understanding is that SCR 7.5 "The size of any register shall be no greater than the width of the containing address block" also applies to virtual registers. Best regards, Erwin
  21. If I create "virtual registers", that is, registers defined inside an addressBlock with usage "memory", does the size of the register still need to be <= the addressBlock width, as mandated by "SCR 7.5 RegisterSizeWithinBlock"?
  22. For analogue signal traces, the tabular trace file format is better suited. Creating them is very similar to VCD trace files. You just need to use sca_util::sca_create_tabular_trace_file() and sca_util::sca_close_tabular_trace_file() to respectively open/close these trace files. The typical file extension is ".dat". These trace files can be easily imported in gnuplot, Octave, MATLAB, Excel, and other mathematical tools for plotting / post-processing. Check out IEEE Std. 1666.1-2016 clause 9.1 for details. Tracing is also discussed in Section 6.2 of the SystemC AMS User's Guide.
  23. I think defparam is partly to blame here. Before introducing the inline parameter override syntax using #(param1,...) in Verilog-2001, it was very difficult to predict when a parameter had received its final elaborated value relative the the module referencing it. Adding generate constructs makes that process even harder when you start allowing hierarchical references to parameters outside you instance, before the instance hierarchy has been fully elaborated. So the "no hierarchical names" rule is a broad hammer. In your particular example, you can get around this rule by using typedef in
  24. You should also take a look at uvm_heartbeat. It might be appropriate.
  25. Oh thanks, just what i was looking for. I'll try it on my environment
  26. Thanks, Is there any periodic event that i can trigger in the SB, then i can go through the items and see if the current time - creation time is large?
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