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  1. Today
  2. Thank you for the explanation, I changed it. To prove your statement I tried it with a static integer, and it is traced correctly. About the remaining bugs, regarding dangling references. Only private member of my class is private: std::vector<int> vec; Access methods return ref to vec or store elements of passed argument inside the local ref, by copying. I added an exception for invalid vector size, to avoid reallocation of vector and thus dangling references. const std::vector<int>& read() const { return vec; } void write(std::vector<int> var) { if (var.size() != 4) { throw std::invalid_argument("Argument is not size 4!"); } this->vec.assign(var.begin(), var.end()); } The assignment operator uses the write method. TraceVector operator= (const TraceVector& var) { write(var.read()); return *this; } I don't see the error where I leave dangling references that would cause the sc_trace mechanism to display wrong values. In sc_main I declare my sc_signal like this typedef TraceVector sim_type; // typedef for swapping signal type in one code line #define SIM_TYPE_INIT std::vector<int>{9999,9999,9999,9999} // different type needs different inits sc_main() { ... sc_signal< sim_type, SC_MANY_WRITERS> test{"test", SIM_TYPE_INIT }; ... sc_trace_file *tf = sc_create_vcd_trace_file("traces"); sc_trace(tf, test, "test"); sc_start(); sc_close_vcd_trace_file(tf); }
  3. It happens because there is no source files ".cpp" when generating libmacros.la. You can work around by creating the dummy file (empty) source file and update the Makefile.
  4. Yesterday
  5. I see at least 1 bug in code sample: for (auto val : var.read()) here you create copies of vector elements on a stack of your function. And then pass references to them into SystemC kernel. So those will be dangling references one you return from your sc_trace overload. Change to: for (auto & val : var.read())
  6. Are you missing the function prototype in the "Cnt_time.h" class ? Or does the parameter list not match with what you implemented in "Cnt_time.cpp"? Btw you for loop wont work like this. A few suggestions. for (int i = 0; i < 20; i++) { wait(20, SC_SEC); cout << i << endl; cout << "INFO: Time is " << sc_time_stamp() << "!" << endl; }
  7. When I add the 'const' keyqord to the reference parameter it works. void sc_trace(sc_trace_file* tf, const TraceList& var, const std::string& nm); // works Additionally I had to change my read method. // Old std::list<int>& read() { return lst; } // New const std::list<int>& read() const { return lst; } I could not trace the values of a list, even when the size of the list remained constant. So I tried it with a vector and created TraceVector. The size of the vector will be 4. There are some size checks missing to ensure this, but that's not what I try to show with this. class TraceVector { private: std::vector<int> vec; public: // Methods for accessing list const std::vector<int>& read() const { return vec; } void write(std::vector<int> var) { this->vec.assign(var.begin(), var.end()); } // CTOR TraceVector() { vec.reserve(4); } // CTOR for init values TraceVector(std::vector<int> var) { vec = var; } // Required by sc_signal<> and sc_fifo<> TraceVector operator= (const TraceVector& var) { write(var.read()); return *this; } // Required by sc_signal<> bool operator== ( const TraceVector& var) const { auto temp = var.read(); // size check if (temp.size() != vec.size()) { return false; } // element wise comparison bool equal = std::equal(vec.begin(), vec.end(), temp.begin()); return equal; } }; // Required functions by SystemC ostream& operator<< (ostream& os, TraceVector var); void sc_trace(sc_trace_file* tf, const TraceVector& var, const std::string& nm); Since I can not store multiple values in one datatype and trace it, I decided to create a trace for each element in the vector. void sc_trace(sc_trace_file* tf, const TraceVector& var, const std::string& nm) { int pos = 0; sc_core::sc_trace(tf, 0, nm + "_test"); for (auto val : var.read()) { // use namespace, compiler otherwise chooses wrong function sc_core::sc_trace(tf, val, nm + "_" + std::to_string(pos++)); } } The result looks like this: The displayed values are not the values from the vector. Even the value of test_test is not 0, even though I set it to a constant 0. Somebody knows why sc_trace is tracing the wrong values?
  8. You call tf->set_time_unit(1, SC_NS); without initializing tf before. Hope that helps, Philipp
  9. Last week
  10. Hi everyone, I've this link problem, it seems thant the linker cannot see some files (i think sc_module.h or sc_time.h). In my opinion systemc library is correctly set. Can someone help me? Maybe a problem with debugger(DebugDll)? Thanks a lot!! -Michael
  11. Avnita


    Hello sir, I wrote and_gate systemc code with test bench and it got compiled, also generated simv but it shows Segmentation fault (core dumped) error. Could you please suggest me what exactly it is and how I will resolve this. #include "systemc.h" //AND gate module SC_MODULE (and_gate) { sc_in <bool> a, b; sc_out <bool> c; //Process for AND gate void and_fun() { c.write(a.read() & b.read()); } //Constructor for AND gate module SC_CTOR (and_gate) { SC_METHOD (and_fun); //process for sesitivity sensitive << a << b; } }; //Testbench for AND gate int sc_main (int argc, char* argv[]) { //testbench signals sc_signal <bool> a, b, c; sc_trace_file *tf; //module instantiation and name based connection and_gate and1 ("and_gate_and1"); and1.a(a); and1.b(b); and1.c(c); tf->set_time_unit(1, SC_NS); a = 0; b = 0; wait(); //sc_start(1.0, SC_NS); //a = 0; //b = 1; //wait(); //sc_start(1.0, SC_NS); //a = 1; //b = 0; //sc_start(1.0, SC_NS); //a = 1; //b = 1; //sc_start(1.0, SC_NS); //sc_stop(); cout << "Finished at time " << sc_time_stamp() << endl; return 0; } [root@silicon SYSTEM_C_FILES]# vi and_gate.cpp [root@silicon SYSTEM_C_FILES]# syscan and_gate.cpp [root@silicon SYSTEM_C_FILES]# vcs -sysc and_gate.cpp make: Entering directory `/home/avnita/Workspace/SYSTEM_C_FILES/csrc' if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath=/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4 -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -rdynamic -Wl,-E -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/sysc_globals.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ucli_sysc.o objs/GdI28_d.o objs/amcQw_d.o amcQwB.o objs/ivVCS_d.o SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/and_gate.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/libcsrc_sysc_stubs.a -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lsysctli -lbfSim -lbfCbug -lsystemc231-gcc4 -lvirsim -lvcsnew -lsimprofile -luclinative /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_tls.o _vcs_pli_stub_.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_save_restore_new.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl ../simv up to date make: Leaving directory `/home/avnita/Workspace/SYSTEM_C_FILES/csrc' [root@silicon SYSTEM_C_FILES]# ./simv -gui Segmentation fault (core dumped)
  12. Compiler already shown you where is the error and how to fix it. SystemC is a C++ library, you will need to learn C++ and get comfortable with g++ compiler before digging into SystemC.
  13. Avnita


    I have written test bench for the above code (and gate) but i am getting some errors. Please guide me that how to write test bench in system C #include "systemc.h" #include "and_a.cpp" SC_MODULE (and_tb) { sc_in <sc_int <8> > a, b; sc_out <sc_int <8> > f; sc_in <bool> clk; void and_gate() { a.read(0); b.read(0); //f.write(0); wait(); a.read(1); b.read(1); //f.write(1); wait(); a.read(0); b.read(1); //f.write(0); wait(); a.read(1); b.read(0); //f.write(0); wait(); sc_stop(); } SC_CTOR (and_tb) { SC_METHOD (and_gate); sensitive << clk.pos(); } }; Output: error message: /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: candidate expects 0 arguments, 1 provided /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:21:9: error: no matching function for call to ‘sc_core::sc_in<sc_dt::sc_int<8> >::read(int)’ b.read(0); ^ /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:21:9: note: candidate is: In file included from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_clock_ports.h:31:0, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc_:54, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc:2, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc_.h:245, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc.h:2, from /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:1: /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: const data_type& sc_core::sc_in<T>::read() const [with T = sc_dt::sc_int<8>; sc_core::sc_in<T>::data_type = sc_dt::sc_int<8>] const data_type& read() const ^ /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: candidate expects 0 arguments, 1 provided gmake: *** [and_tb.o] Error 1
  14. Avnita


    Hello, Thankyou for your advice, I applied sc_main and I got this output mention below as screen shot.
  15. I would suggest to leave this up to the tool vendor. (I don't believe IP-XACT provides any guidelines around this) However I think any tool should only consider optimisation (or/and reporting errors) after all the connections (including inter-connections) have been fully resolved. Kind regards, Edwin
  16. Hi Kushi, In IP-XACT, an interconnect connects the logical port bits that are mapped in the connected bus interfaces. The direction of those logical bits does not matter. So the direction can be in on all end points, and also the component port bits mapped to these logical port bits can all have direction in. In an HDL netlist, this would translate to a net with all inputs at its ends. It depends on the netlister tool that you use whether such a net is actually generated or not. Typically your netlister tool generates a warning or error that you have undriven inputs. However, there is no semantic rule in IP-XACT that forbids undriven inputs. In order to drive such a net, it is sufficient in IP-XACT to connect it somehow to a component output port. This can be done with adhoc connections, additional bus interface connections, and/or phantom ports. This is completely free to decide depending on which IP-XACT design-style you wish to use. Best regards, Erwin
  17. Hi Kushi, The Accellera bus definitions contains files for I2C. There are two: one for I2C internal (uni-directional signals) and one for I2C external (bidirectional signals). They allow you to make direct connections from master to slave. A bus does not have to be symmetric to support direction connections. The bus definition property directConnection determines if you are allowed to make direct master to slave connections or not. Best regards, Erwin
  18. Hi Edwin, I understand your point but if both A.a and B.b map the clock signal and if we just connect A.a to B.b,should the tool connect the clock or not ? with error or without error ?. In general during interface connections, what happens to pins which has same direction on both sides ? Should tool connect them ? or left them unconnected ? with or without error/warning? Thanks Khushi
  19. Hello Kushi, Sorry, there is no official way to achieve this using IP-XACT 2009. Kind regards, Edwin
  20. Hello Kushi, I am not sure I understand why the tool would report an error? Let's say I have instance interface A.a connected to instance interface B.b and I have connected interface B.c to interface c on the top. A specifies clock signal clockA, B specifies clock signal clockB (both interface B.b and B.c map this clock signal) and interface c maps to signal clockTop. This means that clockA is connected to clockB and clockB is connected to clockTop all signals share the direction 'in' which means that clockTop drives this connection (perfectly valid and no need for phantom ports or components). Kind regards, Edwin
  21. Thanks Edwin. Currently we are in IP-Xact 2009. Is there a way to do this in 2009 ? Thanks Khushi
  22. Hi Edwin Thanks for your comment and links to ARM busdefs. I didn't understand the following Normally both clock and reset are "in" on both master and slave interfaces. So when you connect master to slave then - either the tool reports an error saying can not connect two ports with same direction - or ther tool just skip the connections with a warning and later we can do some adhoc connections In your environment, you mentioned the clock and reset physical ports are mapped in component master/slave bus interface with other protocol signals. In this case how you connect these with clock and reset driver without a phantom port ? Thanks Khushi
  23. Hello Kushi, In IP-XACT 2014 you can pass the parameters from component to design, this should enable what you require? Kind regards, Edwin
  24. Hello Khushi, Please use the following link for the latest versions of the AMBA bus-definitions: https://silver.arm.com/browse/AR500 In general I agree with the steps you highlight, our IPs are packaged mapping the clocks and resets in the interface. However I don't believe that this necessarily means that phantom ports or components would be required to be able to connect the clocks and resets for these interfaces, however care must be taken. Kind regards, Edwin
  25. Hi Erwin Thanks for the explanation. It clears a lot of doubts. I really appreciate your efforts. I have one more related questions. If I have a component with I2C master interface and another component with I2C slave interfaces. As I2C interface is asymetric, so I cannot connect master to slave directly. In this case how these two component can be connected. Do we need some extra abstractor/bridge or phantom component with mirrored interfaces here to make the connections ? Thanks Khushi
  26. Hi Erwin, If I see the AMBA busdef AMBA_IP-XACT-1.4_BusDefinitions_2011_10_21\amba.com\AMBA4\AXI4\r0p0_0, I see for both ACLK and ARESETn, the presence element is required in both onMaster and onSlave Here you want to say something else ? =========================================================== To summarize my understanding regarding the clock and reset stuff. -a) We should list the clock and reset in protocol abstraction definition -b) We should set presence => optional for both clock and reset in both onMaster and onSlave -c) In component businterface, we can either map the physical clock and reset to busdef logical ports or not 1) if we map, then we should use phantom component strategy as you explained in ( https://forums.accellera.org/topic/6446-interface-mode-mirroredmaster-mirroredslave/ ) 2) if we not map, then either we connect clock and reset as adhoc or create clock and reset businterface in component and create interface connections for clock and reset (what is recommended here ??) Please let me know if my understanding is correct. Thanks Khushi
  27. Hi I have a design(top) with two instances of a subsystem(ss). In the subsystem(ss) I have an instance of a component(cmp). My design instances looks like top top.ss1 top.ss1.cmp top.ss2 top.ss2.cmp The component (cmp) is a generic component,(lets say a memory which has a generic parameter SIZE and during the instantiation of that component we specify the SIZE for that instance). I created a component and specify the SIZE as model parameter. Then I created a subsystem design with an instance of component cmp and specify the SIZE parameter in IP-Xact design(configurable element value). I instantiate that subsystem as ss1 in top. So far so good. Now I have to instantiated the same subsystem as ss2 in same top and in top.ss2.cmp.SIZE parameter value is different then top.ss1.cmp.SIZE. The cmp SIZE value is specified while creating the cmp instance in subsystem component. Here I stuck because I do not find a way to have different values of top.ss1.cmp.SIZE and top.ss2.cmp.SIZE. Is there a way to do this in Ip-Xact ? Thanks Khushi
  28. VCS invokes g++ automatically. But this is correct, sc_main is missing.
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