adielkhan
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About adielkhan
- Birthday 02/02/1979
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adielkhan
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issue to access hierachy at compile time in VCS
adielkhan replied to uvmcraft's topic in UVM Simulator Specific Issues
move the import and the class outside of the scope of the interface. register the interface using uvm_resource_db set() routine. contact your local support who can help you with the syntax if you need it. -
UVM test simulation using vcs and DVE
adielkhan replied to shireen's topic in UVM Simulator Specific Issues
add the signals to the waveform and view them. your local support can walk you through it or you can look at the tutorials on solvnet.synopsys.com -
Dear all, As we close in on delivering UVM 1.2 to the engineering community now is the time for you to read the docs, review the code, test the functionality. Or as they say forever hold your peace..... Once approved changing documentation requires another full review so really please do give your feedback ASAP. As a UVM user it is in your interest that UVM meets your requirements and your opinion is considered. There is a list of issues we know about within the Mantis database: http://www.eda.org/svdb/my_view_page.php If you want to view the code for a particular branch from sourceforge you can do so from your browser. http://sourceforge.net/p/uvm/code/ref/master/branches/ On the left click ""More Branches" UVM 1.2 will be built from the UVM_1_2 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2/tree/ At the time of writing the latest HTML docs are generated from RC4 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2_RELEASE_RC4_WITHHTMLDOC/tree/ It is just as easy to grab the latest code for you to run with your own projects for testing. A simple script can look like: #!/bin/csh -f mkdir $1; cd $1 ; git clone git://git.code.sf.net/p/uvm/code ; cd code ; git branch --track $1 origin/$1 ; git checkout $1 ; By passing in your branch name to the script it will checkout that particular branch for you. git_uvm.csh UVM_1_2 ; You can give feedback via your Accellera representation or local EDA person or provide feedback here. Time is of the essence so act today. thanks,
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Best Technique to Measure Simulation Times using VCS
adielkhan replied to cliffc's topic in UVM Simulator Specific Issues
hi Cliff, VCS has a bunch of very advanced profilers built in for you to use. like -reportstats -simprofile for memory and time along with constraints profilers. Too many options and mechanism to list here. RTFM I'm afraid. Over the years we have been tweaking the profilers to give better info on what is good and bad for testbenches. At some point we should compare notes on the topic. -adiel -
simple override example - with error
adielkhan replied to ljepson74's topic in UVM SystemVerilog Discussions
the $cast() in the create function fails because orange is not an apple. if you change orange to derive from apple then $cast will succeed. i.e typedef class apple; class orange extends apple; -
Done. http://www.eda.org/svdb/view.php?id=4809
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you mean you dont like typing theRal_block.get_field_by_name().write(); People really want a new API for that oneline statement ? I'd be happier if you said lets get rid of all the *by_name() API's and ensure people use object referencing. The string-type name field of registers and fields is so similar to the actual definition-type of the class that I am yet to see a case where all that string manipulation is worth the poor performance and lack of checking just so you can do some fancy $sformatf().
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Problem about uvm_object_defines.svh ???
adielkhan replied to a topic in UVM Simulator Specific Issues
hi, We run all the UVM examples as part of Accellera testing on VCS, QuestaSim & IUS. If you are seeing issues with the examples please provide more information such as tool versions and any modification you may have made. Also, it is worth opening a support ticket with the tool vendor you are trying to use. -adiel. -
hi, You should file a Mantis to have UVM support diagnostics for $finish as described in 1800-LRM. As a workaround you might be able to code a report_catcher to catch all FATALs and ERRORs then call $finish(arg) .
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Hi VCS 2008.09 is way too old, UVM was not even thought of back then. The current version of VCS is 2013.06 let us know if there are any issues when you use 2013.06 version of VCS. -adiel
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Huge sv file - vcs out of memory
adielkhan replied to seyaleli22's topic in UVM SystemVerilog Discussions
hi Eyal, send the file to vcs_support@synopsys.com they will review and help you devise techniques to avoid such problems. thanks, adiel adiel@synopsys.com -
Problem when setting breakpoint using ucli
adielkhan replied to mrforever's topic in UVM Simulator Specific Issues
hi, Send your testcase to vcs_support and they will resolve the issue for you. All DVE preferences are under the "edit" menu item. -
Out of bound error in UVM 1.1c
adielkhan replied to rajneeshT's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi, You are probably passing a command line arg to enable this check. Look for "–ntb_opts check=all" -
hi, Personally, I dont see why you need the line/filename at all. if you are debugging somethign then bring it up in your gui and double click the message and it will take you to the `uvm_info line being called in your code. Therefore, I compile with the disable FILE_LINE option. However, some people like to see tonnes of messages appear in their logifles and for those they should review Brians' blog: http://www.vmmcentral.org/vmartialarts/2012/04/customizing-uvm-messages-without-getting-a-sunburn/
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Return from function to pass into another function?
adielkhan replied to swapnilm's topic in UVM SystemVerilog Discussions
hi, You need to share some code for us to help you. Something like my_decoder_func().drive() is probably what you want to do.