Adam Sherilog

You have a need for speed. Everyone does. But not a small need. You have a big need. Not a 2X need. A much bigger need. The kind of need that can only be satisfied with Palladium, the best hardware accelerator available. Axel Scherer, my Cadence brother, recorded this video to show how you can run your UVM environment in simulation and acceleration. Spend 5 min to learn how you can quench your need for speed. http://youtu.be/2S4NIrOT9XE?list=PLYdInKVfi0KZqWOWeDTa58tuBD-5S7HQC Fast simulation. Fast acceleration. Fast post. Enjoy. =Adam Sherer, Cadence

Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog

Hi, I think this question, especially for a particular set of product licenses, is best answered by Cadence support. But the IES vs IUS I can answer here. IES, the Incisive Enterprise Simulator, has two product configurations L and XL. The IES-XL is the one you should use if you previously purchased IUS (Incisive Unified Simulator). IES-XL is a whole superset of IUS and can run any scripts created using IUS. =Adam Sherer, Incisive Simulation Product Manager

Folks, We had some complaints about this thread. If there is truly a tools-related issue, that should be directed to the vendor's support team. We shouldn't use these forums to suggest that users of vendor X would be better off with vendor Y. If a vendor has something to promote, that should be handled in the "Simulator Specific" or "Commercial" forums. =Adam Sherer Accellera Promotions Committee Vice-Chair

The DVClub meeting September 9 is 100% dedicated to you all reading this forum -- UVM and SystemVerilog. We'll have four topics in this fast-moving event: Update from the Accellera UVM Working Group UVM Register Modelling: Advanced Topics SystemVerilog Scheduling Semantics Advanced Scoreboarding Techniques Using UVM You can register for the event here: http://dvclubsept2013.eventbrite.com/#! On behalf of the other presenters, we are looking forward to seeing or hearing you there! =Adam Sherer, UVM WG Secretary

One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun. ) =Adam Sherilog, Cadence

You can also find the release notes on the accellera.org site. The 1.1c notes show the delta from 1.1b. By Accellera rules, the [abc*] releases do not change the standard. =Adam

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple language in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. This solution was updated several times during the past four years to remain synchronized with UVM and add new functionality. On Thursday October 25 at 9a PDT we'll review the solution and discuss new features. Join us through this link: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home =Adam Sherer, Cadence

It's here! The UVM 1.1c release is now available for immediate download on the Accellera Website at http://www.accellera.org/downloads/standards/uvm. Enjoy! =Adam Sherer, Accellera VIPTSC Secretary

And just when you thought all of the above goodness was too good to be true, we have even more! UVM has been growing by leaps and bounds in China so we translated the video shorts into Chinese! Do to some restrictions in China, we have made the videos available on two sites: Link to YouTube Playlist (Chinese) Link to YouKu Playlist (Chinese) Link to YouTube Playlist (English) Link to YouKu Playlist (English) We would also like to introduce our third twin :-), Yi-Shiun Lin who did the work to translate these videos. Thank you! =Adam Sherilog on behalf of both of his twins Axel and Yi-Shiun

Just when you thought 24 videos about UVM were enough, we added more! This video walks you through the UVM Class Library pointing out key aspects that are important to all UVM developers. It's your coffee break, so grab a fresh cup and enjoy! http://www.cadence.com/Community/blogs/fv/archive/2012/07/16/uvm-systemverilog-class-library-overview-video-inspired-by-1600-cowbells-in-action.aspx =Adam Sherilog on behalf of Cadence's prolific video presence, and my twin brother, Axel Scherer

The Accellera Systems Initiative Verification IP Technical Subcommittee (aka UVM) has approved the UVM 1.1b for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. We have also had numerous requests to make the release notes and user guide available both inside and outside of the tarball. You can find direct links to both documents on the downloads page and here: UVM 1.1b tarball UVM 1.1b release notes UVM 1.1 user guide UVM 1.1b closes more than 40 Mantis items and represents the combined contributions from multiple committee members. The Chairs would like to thank the worldwide community for their use of UVM and their timing reporting of bugs. =Adam Sherer, VIPTSC (UVM) Secretary

All, Axel Scherer manages a team of UVM experts and has recorded their collected experience in a series of 24 UVM SystemVerilog basics videos. Each video is between 2 and 5 minutes making them easy to view when you have some free time, and easy to review when you're looking for a refresher. The videos are open to all viewers with no registration required. Just a little Cadence EDA360 to help the UVM community. http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE The initial set of topics include the following and we expect to do more in the future: Introducing UVM Example DUT UVM Environment Interface UVC Collector Monitor Sequence Item Sequence Driver Sequencer Agent Agent types Interface UVC environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases Objections Virtual Interface =Adam Sherilog Cadence Verification Product Director

The Accellera Systems Initiative Verification IP Technical Subcommittee (we have ENORMOUS business cards ) has approved the UVM 1.1a for immediate release. You can download it now at http://www.accellera.org/downloads/standards/uvm and the links from UVMWorld are being updated to point to it. UVM 1.1a closes more than 60 Mantis items and represents the combined contributions from multiple committee members. Once again, the team working on UVM proves that industry-wide collaboration not only works but can produce something can makes us all proud. =Adam Sherer, VIPTSC (UVM) Secretary

Wednesday December 7 at 11a ET, Cadence will explain UVM phasing in the cleverly titled "Set Your UVM Runtime Phases to Maximum Power" webinar. The seminar will be delivered by the legendary Uwe Simm whom you all know as a prolific contributor to the UVM technical forums. he Accellera Universal Verification Methodology (UVM), like the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM) before it, divides the overall verification effort into multiple phases. Most of these do not consume simulation time but rather manage the construction and completion of the verification test. The run phase is the one in which time proceeds, tests inject stimulus, and monitors/scoreboards measure the responses. While some UVM verification components (UVCs) are simple enough to view this phase as atomic, others need to finely manage steps such as configuration, reset, and post-run clean-up. The UVM subdivides run and allow you to control testbench activity in each sub-phase. That may seem simple enough, but if your UVC does need these sub-phases, then you need to now manage its integration with UVCs that may or may not use sub-phases. Each UVC may need to jump forward or back through the sub-phases, and that coordination will need to be managed as well. Our verification expert Uwe Simm is the leading contributor to the bugs fixed in UVM and to the questions asked in these forums and will present the following topics: Identifying when UVM runtime phases are really required Basics of the UVM runtime phases – what the UVM BCL provides Applying the runtime phases using the UVM Reference Flow Common problems and solutions when applying runtime phases The webinar will share the steps you need to determine if your UVC really needs runtime phases. If it does, the component is simpler to build and maintain. Assuming you are attending because you do need to apply them, the webinar will provide critical methodology guidelines to maximize the verification power you will derive from runtime phases and help you to avoid common pitfalls as you integrate your UVC into larger system verification environments.