Dynamic memory allocation for typedef

[sanketshah]

I have a typdef enum and I want to declare a variable inside case statement.

can I do following in one of my function?

tx_0, tx_1,tx_2, and tx_3 are user defined enum types.

function my_func(bit [1:0]a)

case(a)

0: tx_0 i = new tx_0; // line 0

1: tx_1 i = new tx_1;

2: tx_2 i = new tx_2;

3: tx_3 i = new tx_3;

endfunction

I have tried this but it shows error "(**** line 0): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)]."

[dave_59]

Can you show ALL the declarations for your code. Just guessing, perhaps you meant

int i[];

typedef enum{tx_0=3,tx_1=5,tx_2=7,tx_3=11 ) tx_t;

function void my_func(bit [1:0]a)

case(a)

0: i = new [tx_0]; // line 0

1: i = new [tx_1];

2: i = new [tx_2];

3: i = new [tx_3];

endcase

endfunction

Can you explain without using SV syntax what you want to do?

[sanketshah]

I have many user defined data types and I want to write a common functions for that. Inside that function I want to create variable or object only for the data type passed to the function argument.

Let me know if you are not clear yet.

[sanketshah]

Can you show ALL the declarations for your code. Just guessing, perhaps you meant

int i[];

typedef enum{tx_0=3,tx_1=5,tx_2=7,tx_3=11 ) tx_t;

typedef enum {i0, i1, i2, i3, i4} inst1;

typedef enum {i0,i7,i8,10,i3} inst2;

typedef enum {i1,i11, i9,i20,i21} inst3;

typedef enum {i0....iall} INST_ALL

typedef enum {INST1,INST2,INST3} inst_all;

function (inst_all inst_all_type, INST_ALL i_all)

case (insta_all_type.name())

INST1: inst1 i = new inst1

INST2: inst2 i = new inst2;

INST3: inst3 i = new inst3;

endcase

// from here operate on variable "i" only

endfunction

[dave_59]

There are no dynamic types in SystemVerilog except for class variables. Perhaps you are going about this the wrong way. May you need to build lists, associate arrays, or queues instead of trying to use enums.

Can you describe some of the operations you want to do with i?

[sanketshah]

As I said inst1, inst2, inst3 are all typedef enums. and I want to iterate through the enum list and find out if it matches i_all which is instruction supplied. i_all is also an instance of all instruction. Basically I want to find out supplied instruction i_all is of which enum type. inst1, inst2, or inst3 ???

[dave_59]

Look at using the inside operator to match a value in an array. That array can be a list of instructions. You can have different arrays that represent different lists of instructions, and then use the inside operator to find out which list a particular instruction matches.

Again, try to describe what you want to do without using any SystemVerilog syntax. What defines an instruction? Don't use the word enum or typedef.

[sanketshah]

I did not understand what did you say using [\B]. Can you please provide an example?

Here is what I am trying to achieve. I have whole list of instructions. Each instruction fits into a particular category. DUT will operate based on the the category of instruction. There is a qualification logic inside DUT. I am trying to verify that logic.

[KathleenMeade]

Hello There,

Your request is confusing because you are trying to do a few things that are not possible with SystemVerilog enumerations. First, you can't have duplicate enumeration identifiers in the same scope so you can't have a composite "all_inst". Second you don't "new" an enumeration. You can create a dynamic array or an associative array or queue of enumerations.

I played around with this a little bit and came up with an associative array of these types. You can probably make it less complicated with a look-up table using int but here is something to get you started.

module test;

//typedef enum {i0, i1, i2, i3, i4} inst1;

//typedef enum {i0, i7, i8, i10, i13} inst2;

//typedef enum {i1, i11, i9, i20, i2} inst3;

typedef enum {i0, i1, i2, i3, i4, i7, i8, i9, i10, i11, i13, i20} all_inst;

typedef enum {INST1, INST2, INST3} inst_type;

all_inst inst1[all_inst] = '{i0:i0, i1:i1, i2:i2, i3:i3, i4:i4};

all_inst inst2[all_inst] = '{i0:i0, i7:i7, i8:i8, i10:i10, i13:i13};

all_inst inst3[all_inst] = '{i1:i1, i11:i11, i9:i9, i20:i20, i2:i2};

function void create_me (input inst_type select_type, all_inst ix,

output all_inst this_i);

case (select_type)

INST1: this_i = inst1[ix];

INST2: this_i = inst2[ix];

INST3: this_i = inst3[ix];

endcase

// from here operate on variable "this_i" only

$display("inst_type=%s ix=%s this_i=%s", select_type.name(),

ix.name(), this_i.name());

endfunction

initial begin

all_inst inst_da[] = new[3];

create_me(INST2, i7, inst_da[0]);

create_me(INST3, i20, inst_da[1]);

create_me(INST1, i4, inst_da[2]);

foreach (inst_da)

$display("inst_da[%0d]=%s", i, inst_da.name());

end

endmodule : test

[sanketshah]

Kathleen: I believe, what you have suggested will solve my issue. Thank you very much for your response.

Dave: Thank you very much for your selfless and instant help.